Datasheet

T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
S
S
S
D
D
D
6
6
6
4
4
4
V
V
V
3
3
3
A
A
A
200PIN DDR333 Unbuffered SO-DIMM
1GB With 64Mx8 CL2.5
AC Timing Parameters & Specifications
(These AC characteristics were tested on the Component)
tCK
tCK
ns
Parameter Symbol Min
Col. Address to Col. Address delay tCCD 1
CK to valid DQS-in tDQSS 0.75
Address and Control input hold time tIH 0.75
Max Unit Note
tCK
1.25 tCK
ns
Row cycle time tRC 60
Clock cycle time tCK 6
DQS-in setup time tWPRES 0
Data-out high-impedance time from CK, /CK tHZ -0.70
ns
12 ns 4
ns 2
+0.70 ns
Refresh row cycle time tRFC 72 ns
0.45 0.55 tCK
tCK
Row active time tRAS
Clock low level width tCL
DQS falling edge to CK rising-setup time tDSS
Mode register set cycle time tMRD
42 120K ns
0.45 0.55 tCK
0.2 tCK
2 tck
/RAS to /CAS delay tRCD
DQS-out access time from CK /CK tDQSCK
DQS falling edge from CK rising-hold time tDSH
DQ & DM setup time to DQS tDS
18 ns
-0.70 0.75 ns
0.2 tCK
0.45 ns
Row active to Row active delay
Output data access time from CK /CK
DQS-in high level width
tRP 18 ns
tAC -0.70 0.75 ns
tDQSH 0.35 tCK
Row active to Row active delay
Data strobe edge to output data edge
DQS-in low level width
tRRD 12
tDQSQ 0.45
tDQSL 0.35
ns
Write recovery time
ns 4
Read Preamble
tCK
DQS-in cycle time
tWR 15
tRPRE 0.9 1.1
tDSC 0.9 1.1
tCK
tCK
tCK
Last data in to Read command tCDLR 1
Read Postamble tRPST 0.4 0.6
Address and Control input setup time tIS 0.75
Clock high level width tCH
DQS-in hold time tWPREH
Data-out low-impedance time from CK, /CK tLZ -0.70
0.25
+0.70 ns
Transcend Information Inc.
8