Datasheet

T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
L
L
L
R
R
R
7
7
7
2
2
2
V
V
V
6
6
6
E
E
E
168PIN PC133 Registered DIMM
1024MB With 64Mx4 CL3
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter Symbol Value Unit Note
/RAS to /CAS delay tRCD(min) 15 ns 1
Row precharge time tRP(min) 20 ns 1
tRAS(min) 45 ns 1 Row active time
tRAS(max) 100 us
Row cycle time tRC(min) 65 ns 1
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to Active delay tDAL 2CLK+20ns
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
Number of valid
output data
CAS latency=3 2
ea 4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter Symbol Value Unit Note
Min Max
CLK cycle time CAS latency=3
t
CC
7.5
1000 ns 1
CLK to valid
output delay
CAS latency=3
tSAC 5.4 ns 1, 2
Output data
hold time
CAS latency=3
tOH
3
ns 1, 2
CLK high pulse width tCH 2.5 ns 3
CLK low pulse width tCL 2.5 ns 3
Input setup time tSS 1.5 ns 3
Input hold time tSH 0.8 ns 3
CLK to output in Low-Z tSLZ 1 ns 2
CLK to output
in Hi-Z
CAS latency=3
tSHZ 5.4 ns 1
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend Information Inc. 8