Datasheet

T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
D
D
D
R
R
R
7
7
7
2
2
2
V
V
V
6
6
6
L
L
L
5
5
5
184Pin DDR266 1U Registered DIMM
1GB With 64Mx4 CL2.5
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Max. Unit Note
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK= tCK min
DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle
IDD0 3,180 mA
Operating current - One bank Active-Read-Precharge; Burst=4;
tRC=tRC min; CL=2.5; tCK=tCK min; VIN=VREF fro DQ,DQS and DM
IDD1 3,540 mA
Percharge power-down standby current; All banks idle;
Power –down mode; CKE = <VIL (max); tCK= tCK min
VIN = VREF
for DQ, DQS and DM
IDD2P 1,650 mA
Precharge Floating standby current; CS# > =VIH (min); All banks idle;
CKE > = VIH (min); tCK=133Mhz for DDR266
Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ, DQS and DM
IDD2F 2,010 mA
Active power - down standby current; one bank active; power-down mode; CKE<=
VIL (max); tCK = tCK min;
VIN = VREF for DQ, DQS and DM
IDD3P 1,920 mA
Active standby current; CS# >= VIH (min); CKE>=VIH (min);
One bank active; active - precharge; tRC=tRASmax; tCK = tCK min;
DQ, DQS and DM inputs changing twice per clock cycle; address and other control
inputs changing once per clock cycle
IDD3N 2,280 mA
Operating current - burst read; Burst length = 2; reads; continuous burst; One
bank active; address and control inputs changing once per clock cycle; CL=2.5 at
tCK = tCK min; 50% of data changing at every burst; lout = 0 mA
IDD4R 4,710 mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One
bank active address and control inputs changing once per clock cycle; CL=2.5 at
tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle, 50% of
input data changing at every burst
IDD4W 5,520 mA
Auto refresh current; tRC = tRFC(min)
IDD5 5,070 mA
Self refresh current; CKE <= 0.2V;
IDD6 558 mA
Orerating current - Four bank operation;
Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7 8,040 mA
Note:
Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading cap.
Transcend Information Inc.
6