Datasheet

J
J
J
M
M
M
3
3
3
3
3
3
4
4
4
S
S
S
6
6
6
4
4
4
3
3
3
A
A
A
-
-
-
7
7
7
5
5
5
256MB 168PIN PC133 CL3
SDRAM DIMM With 32M X 8 3.3VOLT
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter Symbol Min Max Unit Note
CLK cycle time
CAS latency=3
tCC
7.5
1000 ns 1
CLK to valid
output delay
CAS latency=3
t
SAC
5.4
ns 1, 2
Output data
hold time
CAS latency=3
t
OH
2.7
ns 2
CLK high pulse width tCH 2.5 ns 3
CLK low pulse width tCL 2.5 ns 3
Input setup time tSS 1.5 ns 3
Input hold time tSH 0.8 ns 3
CLK to output in Low-Z tSLZ 1 ns 2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
5.4
ns
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc. 8