Datasheet

3
T5557
4517E–RFID–02/03
Power-On Reset (POR) This circuit delays the IDIC functionality until an acceptable voltage threshold has been
reached.
Clock Extraction The clock extraction circuit uses the external RF signal as its internal clock source.
Controller The control-logic module executes the following functions:
• Load-mode register with configuration data from EEPROM block 0 after power-on
and also during reading
• Control memory access (read, write)
• Handle write data transmission and write error modes
• The first two bits of the reader to tag data stream are the opcode, e.g., write, direct
access or reset
• In password mode, the 32 bits received after the opcode are compared with the
password stored in memory block 7
Mode Register The mode register stores the configuration data from the EEPROM block 0. It is
continually refreshed at the start of every block read and (re-)loaded after any POR
event or reset command. On delivery the mode register is preprogrammed with the
value ‘0014 8000’h which corresponds to continuous read of block 0, Manchester
coded, RF/64.
Figure 3. Block 0 Configuration Mapping – e5550 Compatibility Mode
000
001
010
011
100
101
110
111
RF/8
RF/16
RF/32
RF/40
RF/50
RF/64
RF/100
RF/128
ST-Sequence Terminator
Safer Key
Note 1), 2)
L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Data
Bit Rate
00
01
10
11
RF/2
RF/4
RF/8
Res.
00000
00001
00010
00011
00100
00101
00110
00111
01000
10000
11000
Direct
PSK1
PSK2
PSK3
FSK1
FSK2
FSK1a
FSK2a
Manchester
Biphase('50)
Reserved
PSK-
CF
AOR
MAX-
BLOCK
1) If Master Key = 6 then test mode write commands are ignored
2) If Master Key <> 6 or 9 then extended function mode is disabled
Modulation
0 Unlocked
1 Locked
Lock Bit
PWD
POR delay