User Guide

2.4 System Board Troubleshooting 2 Troubleshooting Procedures
Table 2-3 D port status (3/9)
D port
status
Inspection items Details
F100h Disabling cache
Initializing H/W (before recognizing DRAM)
Initializing MCHM
Initializing ICH4M.D31.Func0
Initializing ICH4M.D31.Func1
Initializing USB.Func0,1,2,7
Initializing ICH4M.D31.Func3
Initializing ICH4M.D31.Func5
Initializing FLUTE
Initializing the channel 1 of a PIT
(set 30 µs for refresh interval)
F101h Checking type and size of DRAM (at Cold boot only)
HLT when DRAM size is 0
Testing stack area of SM-RAM
HLT when impossible to use as stack
F102h CMOS check and initialization Cache Configuration
Enabling L1 and L2 cache
Access test of CMOS (at Cold boot only)
(HLT when an error occurred)
Checking battery level of CMOS
CheckSum check of CMOS
Initializing CMOS data (1)
Setting up IRT status (Setting of Boot status and IRT Busy
Flag, The bit left is 0)
Storing DRAM size
F103h Resume branch check Not resuming when a CMOS error occurred
(at Cold boot only) Not resuming when status code of resume is not set
Checking resume error
S3 Return error (ICH) Resume error F17AH
Checking CheckSum of SM-RAM
Resume error F173H
Satellite A50/TECRA A2 Maintenance Manual (960-478) 2-23