Datasheet

Intel® Xeon™ Processor with 512 KB L2 Cache
54 Datasheet
NOTES:
1. These specifications are measured at the processor pad.
2. BCLK period is 10 nS.
3. WIRED OR processor signals can tolerate upto 1 V of overshoot/undershoot.
4. AF is referenced to BCLK[1:0].
NOTES:
1. These specifications are measured at the processor pad.
2. These signals are assumed in a 33 MHz time domain.
Table 26. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Duration (ns)
AF = 1
Pulse
Duration (ns)
AF = 0.1
Pulse
Duration (ns)
AF = 0.01
1.80 - 0.320 0.06 0.58 5.77
1.75 - 0.270 0.12 1.25 12.49
1.70 - 0.220 0.35 3.50 20.00
1.65 - 0.170 1.01 10.12 20.00
1.60 - 0.120 3.04 20.00 20.00
1.55 - 0.07 10.16 20.00 20.00
Table 27. Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/Undershoot
Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Duration (ns)
AF = 1
Pulse
Duration (ns)
AF = 0.1
Pulse
Duration (ns)
AF = 0.01
1.80 - 0.320 0.17 1.73 17.30
1.75 - 0.270 0.37 3.75 37.48
1.70 - 0.220 1.05 10.51 60.00
1.65 - 0.170 3.04 30.37 60.00
1.60 - 0.120 9.13 60.00 60.00
1.55 - 0.07 30.48 60.00 60.00