Datasheet

Contents
Datasheet 5
Figures
1 Typical VCCIOPLL, VCCA and VSSA Power Distribution ........................................................18
2 Phase Lock Loop (PLL) Filter Requirements ............................................................................19
3 Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID =1.5V)........................27
4 Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID = 1.525V)...................28
5 Electrical Test Circuit.................................................................................................................37
6 TCK Clock Waveform................................................................................................................37
7 Differential Clock Waveform......................................................................................................38
8 Differential Clock Crosspoint Specification................................................................................38
9 Front Side Bus Common Clock Valid Delay Timing Waveform.................................................39
10 Front Side Bus Source Synchronous 2X (Address) Timing Waveform.....................................39
11 Front Side Bus Source Synchronous 4X (Data) Timing Waveform...........................................40
12 Front Side Bus Reset and Configuration Timing Waveform......................................................41
13 Power-On Reset and Configuration Timing Waveform .............................................................41
14 TAP Valid Delay Timing Waveform...........................................................................................42
15 Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform.........................42
16 THERMTRIP# to VCC Timing...................................................................................................42
17 SMBus Timing Waveform..........................................................................................................43
18 SMBus Valid Delay Timing Waveform ......................................................................................43
19 Example 3.3 VDC/SM_VCC Sequencing..................................................................................44
20 BCLK[1:0] Signal Integrity Waveform........................................................................................46
21 Low-to-High Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+
Buffers ......................................................................................................................................47
22 High-to-Low Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+
Buffers ......................................................................................................................................48
23 Low-to-High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers ........48
24 High-to-Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers.49
25 Maximum Acceptable Overshoot/Undershoot Waveform .........................................................55
26 INT-mPGA Processor Package Assembly Drawing (Includes Socket).....................................57
27 INT-mPGA Processor Package Top View: Component Placement Detail................................58
28 INT-mPGA Processor Package Drawing ..................................................................................59
29 INT-mPGA Processor Package Top View: Component Height Keep-in ...................................60
30 INT-mPGA Processor Package Cross Section View: Pin Side Component Keep-in................60
31 INT-mPGA Processor Package: Pin Detail ...............................................................................61
32 IHS Flatness and Tilt Drawing...................................................................................................62
33 Processor Top-Side Markings...................................................................................................64
34 Processor Bottom-Side Markings..............................................................................................64
35 Processor Pin Out Diagram: Top View......................................................................................65
36 Processor Pin Out Diagram: Bottom View ................................................................................66
37 Processor with Thermal and Mechanical Components - Exploded View..................................95
38 Processor Thermal Design Power vs Electrical Projections for VID = 1.500V..........................96
39 Processor Thermal Design Power vs Electrical Projections for VID = 1.525V..........................97
40 Thermal Measurement Point for Processor TCASE..................................................................98
41 Stop Clock State Machine.......................................................................................................100
42 Logical Schematic of SMBus Circuitry ....................................................................................104
43 Mechanical Representation of the Boxed Processor Passive Heatsink for 3 GHz processors
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