Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet 49
Figure 24. High-to-Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers
0.5 * Vcc
Vt+ (min)
Vt- (max)
Vcc
Vss
Vt- (min)
Threshold Region to switch
receiver to a logic 0.
Allowable Ringback
