Datasheet

Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet 43
Figure 17. SMBus Timing Waveform
Data
Clk
P P
SS
STOP STOPSTART START
t
LOW
t
R
t
HD;STA
t
HD;DAT
t
BUF
HIGH
t
t
SU;DAT
t
t
SU;STA
t
HD;STA
SU;STO
t
F
t
LOW
t
HIGH
T72
=
t
R
T74
=
T73
=
t
F
T75
=
t
HD;STA
t
HD;DAT
T78=
t
BUF
T79=
T80=
t
SU;DAT
T77=
t
SU;STA
T81
=
t
SU;STD
T82
=
Figure 18. SMBus Valid Delay Timing Waveform
DATA OUTPUT
DATA VALID
SM_CLK
SM_DAT
TAA
TAA = T76