Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet 35
Table 18. Front Side Bus AC Specifications (Reset Conditions)
1. Before the de-assertion of RESET#
2. After the clock that de-asserts RESET#.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5 * V
CC
at the processor pins. All
TAP signal timings (TMS, TDI, etc) are referenced at the 0.5 * V
CC
processor pins.
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the rising edge of TCK.
6. Referenced to the falling edge of TCK.
7. Specification for a minimum swing defined between TAP 20% to 80%. This assumes a minimum edge rate of
0.5 V/nS.
8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
9. It is recommended that TMS be asserted while TRST# is being deasserted..
T# Parameter Min Max Unit Figure Notes
T45: Reset Configuration Signals (A[31:3]#,
BR[3:0]#, INIT#, SMI#) Setup Time
4BCLKs12 1
T46: Reset Configuration Signals (A[31:3]#,
BR[3:0]#, INIT#, SMI#) Hold Time
220BCLKs12 2
Table 19. TAP Signal Group AC Specifications
T# Parameter Min Max Unit Figure
Notes
1,2,3,9
T55: TCK Period 60.0 nS 6
T56: TCK Rise Time 9.5 nS 6 4
T57: TCK Fall Time 9.5 nS 6 4
T58: TMS, TDI Rise Time 8.5 nS 6 4
T59: TMS, TDI Fall Time 8.5 nS 6 4
T61: TDI, TMS Setup Time 0 nS 14 5, 7
T62: TDI, TMS Hold Time 3.0 nS 14 5, 7
T63: TDO Clock to Output Delay 0.5 3.5 nS 14 6
T64: TRST# Assert Time 2.0 T
TCK
15 8
Table 20. SMBus Signal Group AC Specifications (Page 1 of 2)
T# Parameter Min Max Unit Figure Notes
T70: SM_CLK Frequency 10 100 KHz 1, 2, 3
T71: SM_CLK Period 10 100 µS 1, 2, 3
T72: SM_CLK High Time 4.0 N/A µS 17 1, 2, 3
T73: SM_CLK Low Time 4.7 N/A µS 17 1, 2, 3
T74: SMBus Rise Time 0.02 1.0 µS 17 1, 2, 3, 5
T75: SMBus Fall Time 0.02 0.3 µS 17 1, 2, 3, 5
T76: SMBus Output Valid Delay 0.1 4.5 µS 18 1, 2, 3
T77: SMBus Input Setup Time 250 N/A nS 17 1, 2, 3
T78: SMBus Input Hold Time 300 N/A nS 17 1, 2, 3