Datasheet

Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet 23
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 4 identifies which signals are common
clock, source synchronous and asynchronous.
1. Refer to Section 5.2 for signal descriptions.
2. These signal groups are not terminated by the processor. Refer the ITP700 Debug Port Design Guide and
corresponding Design Guide for termination requirements and further details.
3. The Intel
®
Xeon™ processor with 512 KB L2 cache utilizes only BR0# and BR1#. BR2# and BR3# are not
driven by the processor but must be terminated to V
CC
. For additional details regarding the BR[3:0]# signals,
see Section 5.2 and Section 7.1 and the appropriate Platform Design Guidelines.
4. These signals do not have on-die termination. Refer to corresponding Platform Design Guidelines for
termination requirements.
5. Note that Reset initialization function of these pins is now a software function on the Intel
®
Xeon™
processor with 512 KB L2 cache.
6. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration
options. See Section 7.1 for details.
7. These signals may be driven simultaneously by multiple agents (wired-or).
8. These signals are not terminated by the processor’s on-die termination. However, some signals in this group
include termination on the processor interposer. See Section 7.4 for details.
Table 4. Front Side Bus Signal Groups
Signal Group Type Signals
1
AGTL+ Common Clock Input Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#
3,4
, DEFER#, RESET#
4
,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#
7
, BNR#
7
,
BPM[5:0]#
2
, BR0#
2
, DBSY#, DP[3:0]#,
DRDY#, HIT#
7
, HITM#
7
, LOCK#, MCERR#
7
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
AGTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+ Input
4
Asynchronous
A20M#
5
, IGNNE#
5
, INIT#
6
, LINT0/INTR
5
,
LINT1/NMI
5
, SMI#
6
, SLP#, STPCLK#
Asynchronous GTL+ Output
4
Asynchronous FERR#, IERR#, THERMTRIP#, PROCHOT#
Front Side Bus Clock Clock BCLK1, BCLK0
TAP Input
2
Synchronous to TCK TCK, TDI, TMS, TRST#
TAP Output
2
Synchronous to TCK TDO
SMBus Interface
8
Synchronous to SM_CLK
SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT,
SM_CLK, SM_ALERT#, SM_WP
Power/Other Power/Other
BSEL[1:0], COMP[1:0], GTLREF, ODTEN,
Reserved, SKTOCC#, TESTHI[6:0],VID[4:0],
V
CC
, SM_V
CC
9
, V
CCA
, V
CCIOPLL
, V
SSA
, V
SS
,
V
CCSENSE
, V
SSSENSE,
PWRGOOD
Signals Associated Strobe
REQ[4:0]#,A[16:3]#
6
ADSTB0#
A[35:17]#
5
ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#