Datasheet

Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet 113
be cleared once the SMBus master device first reads the status register then reads the slave ARA
unless the fault condition persists. Reading the Status Register alone or setting the mask bit within
the Configuration Register does not clear the interrupt.
7.4.8 SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of the form
“1010XXXZb”. The “XXX” bits are defined by pullups and pulldowns on the system baseboard.
These address pins are pulled down weakly (10 K
Ω) on the processor substrate to ensure that the
memory components are in a known state in systems which do not support the SMBus, or only
support a partial implementation. The “Z” bit is the read/write bit for the serial bus transaction.
The thermal sensor internally decodes one of three upper address patterns from the bus of the form
“0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing, as implemented, uses
the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state. Therefore, the thermal sensor supports
nine unique addresses. To set either pin for the Hi-Z state, the pin must be left floating. As before,
the “Z” bit is the read/write bit for the serial transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be generated by an
SMBus master. The thermal sensor samples and latches the SM_TS_A[1:0] signals at power-up
and at the starting point of every conversion. System designers should ensure that these signals are
at valid input levels before the thermal sensor powers up. This should be done by pulling the pins to
SM_V
CC
or V
SS
via a 1 KΩ or smaller resistor, or leaving the pins floating to achieve the Hi-Z
state. If the designer desires to drive the SM_TS_A[1:0] pins with logic, the designer must ensure
that the pins are at input levels of 3.3V or 0V before SM_V
CC
begins to ramp. The system designer
must also ensure that their particular implementation does not add excessive capacitance to the
address inputs. Excess capacitance at the address inputs may cause address recognition problems.
Refer to the appropriate platform design guidelines document and the System Management Bus
Specification.
Figure 42 on page 104 shows a logical diagram of the pin connections. Table 56 and Table 57
describe the address pin connections and how they affect the addressing of the devices.