Datasheet

Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet 109
Table 49. Send Byte SMBus PacketReceive Byte SMBus Packet
Table 50. ARA SMBus Packet
NOTE:
1. This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in the seven most signifi-
cant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See Section 7.4.8 for details on the Thermal Sensor
Device addressing.
Table 51. SMBus Thermal Sensor Command Byte Bit Assignments
S Slave Address Read Ack Command Code Ack P
17-bits118-bits11
S Slave Address Read Ack Data /// P
17-bits11 8-bits 1 1
S ARA Read Ack Address /// P
1 0001 100 1 1 Device Address
1
11
Register Command Reset State Function
RESERVED 00h RESERVED Reserved for future use
TRR 01h 0000 0000 Read processor core thermal diode
RS 02h N/A Read status byte (flags, busy signal)
RC 03h 00XX XXXX Read configuration byte
RCR 04h 0000 0010 Read conversion rate byte
RESERVED 05h RESERVED Reserved for future use
RESERVED 06h RESERVED Reserved for future use
RRHL 07h 0111 1111
Read processor core thermal diode T
HIGH
limit
RRLL 08h 1100 1001
Read processor core thermal diode T
LOW
limit
WC 09h N/A Write configuration byte
WCR 0Ah N/A Write conversion rate byte
RESERVED 0Bh RESERVED Reserved for future use
RESERVED 0Ch RESERVED Reserved for future use
WRHL 0Dh N/A
Write processor core thermal diode T
HIGH
limit
WRLL 0Eh N/A
Write processor core thermal diode T
LOW
limit
OSHT 0Fh N/A One shot command (use send byte packet)
RESERVED 10h – FFh N/A Reserved for future use