Datasheet

Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet 105
Table 44. Processor Information ROM Format (Page 1 of 2)
Offset/Section
# of
Bits
Function Notes
Header:
00h 8 Data Format Revision Two 4-bit hex digits
01 - 02h 16 EEPROM Size Size in bytes (MSB first)
03h 8 Processor Data Address Byte pointer, 00h if not present
04h 8
Processor Core Data
Address
Byte pointer, 00h if not present
05h 8 L3 Cache Data Address Byte pointer, 00h if not present
06h 8 Package Data Address Byte pointer, 00h if not present
07h 8 Part Number Data Address Byte pointer, 00h if not present
08h 8
Thermal Reference Data
Address
Byte pointer, 00h if not present
09h 8 Feature Data Address Byte pointer, 00h if not present
0Ah 8 Other Data Address Byte pointer, 00h if not present
0Bh 16 Reserved Reserved
0Dh 8 Checksum 1 byte checksum
Processor Data:
0E - 13h 48 S-spec Number Six 8-bit ASCII characters
14h
6
2
Reserved
Sample/Production
Reserved (most significant bits)
00b=Sample only, 01-11b=Production
15h 8 Checksum 1 byte checksum
Processor Core Data:
16 - 17h 2 Processor Core Type From CPUID
4 Processor Core Family From CPUID
4 Processor Core Model From CPUID
4 Processor Core Stepping From CPUID
2 Reserved Reserved
18 - 19h 16 Reserved Reserved
1A - 1Bh 16 Front Side Bus Speed 16-bit binary number (in MHz)
1Ch
2
6
Multiprocessor Support
Reserved
00b=UP, 01b=DP, 10b=RSVD, 11b=MP
Reserved
1D - 1Eh 16 Maximum Core Frequency 16-bit binary number (in MHz)
1F - 20h 16 Processor VID (Voltage ID) Voltage requested by VID outputs in mV
21 - 22h 16 Core Voltage, Minimum Minimum processor DC Vcc spec in mV
23h8T
CASE
Maximum Maximum case temperature spec in °C
24h 8 Checksum 1 byte checksum
Cache Data:
25 - 26h 16 Reserved Reserved
27-28h 16 L2 Cache Size 16-bit binary number (in KB)