Intel® Xeon™ Processor with 512-KB L2 Cache at 1.80 GHz to 3 GHz Datasheet Product Features • • • • • • • • • • Available at 1.80, 2, 2.20, 2.40, 2.60, 2.80, and 3 GHz Dual processing server/workstation support Binary compatible with applications running on previous members of Intel’s IA32 microprocessor line Intel® NetBurst™ micro-architecture Hyper-Threading Technology — Hardware support for multithreaded applications 400 MHz Front Side Bus — Bandwidth up to 3.
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Contents Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Introduction....................................................................................................................................11 1.1 Terminology ......................................................................................................................12 1.2 State of Data.....................................................................................................................13 1.3 References .................
Contents 9.0 4 8.4 Thermal Specifications ................................................................................................... 127 Debug Tools Specifications ......................................................................................................... 128 9.1 Logic Analyzer Interface (LAI) ........................................................................................
Contents Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Typical VCCIOPLL, VCCA and VSSA Power Distribution ........................................................18 Phase Lock Loop (PLL) Filter Requirements ............................................................................19 Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID =1.5V)........................
Contents 44 sors 45 46 47 48 49 50 51 52 6 Mechanical Representation of the Boxed Processor Passive Heatsink for 2 - 2.80 GHz proces................................................................................................................................................ 116 Retention Mechanism ............................................................................................................. 118 Boxed Processor Clip..........................................................................
Contents Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Front Side Bus-to-Core Frequency Ratio ......................................................................................17 Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0] ..............................................17 Voltage Identification Definition ....................................................................................
Contents 56 57 58 59 8 Thermal Sensor SMBus Addressing ........................................................................................... 114 Memory Device SMBus Addressing ............................................................................................ 114 Fan Cable Connector Requirements ........................................................................................... 122 Fan Power and Signal Specifications .................................................................
Revision History Date of Release Revision No. January 2002 -001 Initial datasheet release. April 2002 -002 Addition of 2.40 GHz Data May 2002 -003 September 2002 -004 September 2002 -005 Description Updated Figures 10 and 11 Made PWRGOOD updates Addition of 2.60 and 2.80 GHz Data Updated Thermal Requirements Updated Thermal Requirements Updated Table 6, 7 Added Table 12 February 2003 Datasheet -006 Added 3 GHz information. Edited definitions with current terminology.
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache 1.0 Introduction The Intel® Xeon™ processor with 512 KB L2 cache is based on the Intel® NetBurst™ microarchitecture, which operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of IA-32 processors. While based on the Intel NetBurst micro-architecture, it maintains the tradition of compatibility with IA-32 software.
Intel® Xeon™ Processor with 512 KB L2 Cache The Intel Xeon processor with 512 KB L2 cache uses a scalable front side bus protocol referred to as the “front side bus” in this document. The processor front side bus utilizes a split-transaction, deferred reply protocol similar to that introduced by the Pentium® Pro processor front side bus, but is not compatible with the Pentium Pro processor front side bus.
Intel® Xeon™ Processor with 512 KB L2 Cache • Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal solution to the processor. • Interposer - The structure on which the processor core package and I/O pins are mounted. • OEM - Original Equipment Manufacturer. • Processor core - The processor’s execution engine. All AC timing and signal integrity specifications are to the pads of the processor core.
Intel® Xeon™ Processor with 512 KB L2 Cache 1.3 References The reader of this specification should also be familiar with material and concepts presented in the following documents:.
Intel® Xeon™ Processor with 512 KB L2 Cache 2.0 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Intel® Xeon™ processor with 512 KB L2 cache front side bus signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. The processor termination voltage level is VCC, the operating voltage of the processor core.
Intel® Xeon™ Processor with 512 KB L2 Cache Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 6. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines. 2.3.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 1. 2.4.1 Front Side Bus-to-Core Frequency Ratio Front Side Bus-to-Core Frequency Ratio Core Frequency 1/16 1.60 GHz 1/17 1.70 GHz 1/18 1.80 GHz 1/19 1.90 GHz 1/20 2 GHz 1/21 2.10 GHz 1/22 2.20 GHz 1/24 2.40 GHz 1/26 2.60 GHz 1/28 2.80 GHz 1/30 3 GHz Bus Clock The front side bus frequency is set to the maximum supported by the individual processor. BSEL[1:0] are outputs used to select the front side bus frequency.
Intel® Xeon™ Processor with 512 KB L2 Cache The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or CIO in Figure 1), is as follows: • • • • < 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements) > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 2. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB -0.5 dB forbidden zone -28 dB forbidden zone -34 dB DC 1 Hz fpeak 1 MHz passband 66 MHz fcore high frequency band NOTES: 1. Diagram not to scale. 2. No specifications for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 2.5.
Intel® Xeon™ Processor with 512 KB L2 Cache 2.6 Voltage Identification The VID specification for the processor is defined in this datasheet, and is supported by power delivery solutions designed according to the Dual Intel® Xeon TM Processor Voltage Regulator Down (VRD) Design Guidelines, VRM 9.0 DC-DC Converter Design Guidelines, and VRM 9.1 DC-DC Converter Design Guidelines. The minimum voltage is provided in Table 6, and varies with processor frequency.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 3. Voltage Identification Definition Processor Pins 2.6.1 VID4 VID3 VID2 VID1 VID0 VCC_VID (V) 1 1 1 1 1 VRM output off 1 1 1 1 0 1.100 1 1 1 0 1 1.125 1 1 1 0 0 1.150 1 1 0 1 1 1.175 1 1 0 1 0 1.200 1 1 0 0 1 1.225 1 1 0 0 0 1.250 1 0 1 1 1 1.275 1 0 1 1 0 1.300 1 0 1 0 1 1.325 1 0 1 0 0 1.350 1 0 0 1 1 1.375 1 0 0 1 0 1.400 1 0 0 0 1 1.425 1 0 0 0 0 1.
Intel® Xeon™ Processor with 512 KB L2 Cache 2.7 Reserved Or Unused Pins All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to VCC, VSS, or to any other signal (including one another) can result in component malfunction or incompatibility with future processors. See Chapter 5.0 for a pin listing of the processor and for the location of all Reserved pins.
Intel® Xeon™ Processor with 512 KB L2 Cache rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous and asynchronous. Table 4.
Intel® Xeon™ Processor with 512 KB L2 Cache 9. SM_Vcc is required for correct VID logic operation of the Intel® Xeon™ processor with 512 KB L2 cache. Refer to Figure 19 for details. 2.9 Asynchronous GTL+ Signals The Intel® Xeon™ processor with 512 KB L2 cache does not utilize CMOS voltage levels on any signals that connect to the processor silicon. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers.
Intel® Xeon™ Processor with 512 KB L2 Cache 2.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5.1 for the processor pin listings and Section 5.2 for the signal definitions. The voltage and current specifications for all versions of the processor are detailed in Table 6. For platform planning refer to Figure 3.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 6. Voltage and Current Specifications Symbol Parameter VCC for Intel Xeon processor with 512 KB L2 cache VCC SMBus supply voltage SM_VCC Core Freq Min 1.80 GHz 2.0 GHz Max VID Unit Notes1 1.361 1.465 1.5 V 2, 3, 4, 11, 12 1.357 1.463 1.5 V 2, 3, 4, 11, 12 2.20 GHz 1.352 1.46 1.5 V 2, 3, 4, 11, 12 2.40 GHz 1.347 1.458 1.5 V 2, 3, 4, 11, 12 2.60 GHz 1.339 1.453 1.5 V 2, 3, 4, 11, 12 2.80 GHz 1.335 1.450 1.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 3. Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID =1.5V) Maximum Processor Voltage (VDC) 1.51 1.50 1.49 1.48 1.47 1.46 1.45 1.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 4. Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID = 1.525V) Table 7. Front Side Bus Differential BCLK Specifications Notes Symbol Parameter Min Typ Max Unit Figure VL Input Low Voltage -.150 0.000 N/A V 7 VH Input High Voltage 0.660 0.710 0.850 V 7 VCROSS( Absolute Crossing Point 0.250 N/A 0.550 V 7, 8 2,8 0.5(VHavg 0.710) N/A 0.5(VHavg 0.710) V 7, 8 2,3,8,9 N/A N/A 0.
Intel® Xeon™ Processor with 512 KB L2 Cache 4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8.
Intel® Xeon™ Processor with 512 KB L2 Cache 3. 4. 5. 6. TAP signal group must meet the system signal quality specification in Chapter 3.0. Refer to the Intel® Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics. The VCC referred to in these specifications refers to instantaneous VCC. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 7. VOL_MAX of 0.300V is guaranteed when driving a test load.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 12. BSEL[1:0] and VID[4:0] DC Specifications Symbol Parameter Min Max Unit Notes1 Ron (BSEL) Buffer On Resistance 9.2 14.3 Ω 2 Ron (VID) Buffer On Resistance 7.8 12.8 Ω 2 IHI Pin Leakage Hi N/A 100 µA 3 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to Vss with pin held at 2.50V. 2.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 13. AGTL+ Bus Voltage Definitions COMP[1:0] New Design COMP Resistance 49.55 50 50.45 Ω 5, 7, 8 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of VCC. 3. GTLREF is generated from VCC on the baseboard by a voltage divider of 1 percent resistors.
Intel® Xeon™ Processor with 512 KB L2 Cache 2. The processor core clock frequency is derived from BCLK. 3. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2). 4. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines. 5. In this context, period stability is defined as the worst case timing difference between successive crossover voltages.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 16. Front Side Bus Source Synchronous AC Specifications (Page 2 of 2) T# Parameter Min T29: TFDSS: First Data Strobe to Subsequent Strobes Max Unit Figure Notes n/4 BCLKs 11 1, 2, 3, 4, 11, 12, 14 T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay 8.80 10.20 nS 11 1, 2, 3, 4, 13 T31: Address Strobe Output Valid Delay 2.27 4.23 nS 10 1, 2, 3, 4 1.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 18. Front Side Bus AC Specifications (Reset Conditions) T# Parameter Min Max Unit Figure Notes BCLKs 12 1 T45: Reset Configuration Signals (A[31:3]#, BR[3:0]#, INIT#, SMI#) Setup Time 4 T46: Reset Configuration Signals (A[31:3]#, BR[3:0]#, INIT#, SMI#) Hold Time 2 20 BCLKs 12 2 Min Max Unit Figure Notes 1,2,3,9 nS 6 1. Before the de-assertion of RESET# 2. After the clock that de-asserts RESET#. Table 19.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 20. SMBus Signal Group AC Specifications (Page 2 of 2) T# Parameter Min Max Unit Figure Notes T79: Bus Free Time 4.7 N/A µS 17 1, 2, 3, 4, 6 T80: Hold Time after Repeated Start Condition 4.0 N/A µS 17 1, 2, 3 T81: Repeated Start Condition Setup Time 4.7 N/A µS 17 1, 2, 3 T82: Stop Condition Setup Time 4.0 N/A µS 17 1, 2, 3 1.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 5. Electrical Test Circuit Vtt Vtt Rload = 50 ohms Zo = 50 ohms, d=420mils, So=169ps/in L = 2.4nH C = 1.2pF AC Timings specified at pad. Figure 6. TCK Clock Waveform tr *V2 *V3 CLK *V1 tf tp Tr Tf = T56, T58 (Rise Time) = T57, T59 (Fall Time) Tp = T55 (Period) V1, V2: For rise and fall times, TCK is measured between 20%to 80%points on the waveform. V3: Datasheet TCK is referenced to 0.5* Vcc.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 7. Differential Clock Waveform Tph Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tpl Tp Tp = T1 (BCLK[1:0] period) T2 = BCLK[1:0] Period stability (not shown) Tph =T3 (BCLK[1:0] pulse high time) Tpl = T4 (BCLK[1:0] pulse low time) T5 = BCLK[1:0] rise time through the threshold region T6 = BCLK[1:0] fall time through the threshold region Figure 8.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 9. Front Side Bus Common Clock Valid Delay Timing Waveform T0 T1 T2 BCLK1 BCLK0 TP Common Clock Signal (@ driver) valid valid TQ TR Common Clock Signal (@ receiver) valid TP = T10: Common Clock Output Valid Delay TQ = T11: Common Clock Input Setup TR = T12: Common Clock Input Hold Time Figure 10.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 11. Front Side Bus Source Synchronous 4X (Data) Timing Waveform T0 1/4 BCLK 1/2 BCLK T1 3/4 BCLK T2 BCLK1 BCLK0 DSTBp# (@ driver) TH DSTBn# (@ driver) TA TB TA TD D# (@ driver) DSTBp# (@ receiver) TJ DSTBn# (@ receiver) TC D# (@ receiver) TE TG TE TG TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 12. Front Side Bus Reset and Configuration Timing Waveform BLCK Tu Tt RESET# Tv Tx Configuration (A[31:3]#, BR0#, SMI#, INIT#) Safe Valid Tw Configuration (A[31:3]#, BR0#, SMI#, INIT#) Valid Tv = T13 (RESET# Pluse Width) Tw = T45 (Reset Configuration Signals (A[14:5]#, BR0#, SMI#, INIT#) Setup Time) Tx = T46 (Reset Configuration signals (A[14:5]#, BR0#, SMI#, INIT#) Hold Time) Figure 13.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 14. TAP Valid Delay Timing Waveform V TCK Tx Ts Th Signal V Valid Tx = T63 (Valid Time) Ts = T61 (Setup Time) Th = T62 (Hold Time) V = 0.5 * Vcc Figure 15. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T = T64 (TRST# Pulse Width), V=0.5*Vcc q T38 (PROCHOT# Pulse Width), V=GTLREF Figure 16. THERMTRIP# to VCC Timing THERMTRIP# Power Down Sequence T39 THERMTRIP# Vcc T39 < 0.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 17. SMBus Timing Waveform t t LOW t R F t HD;STA Clk t HD;STA t t HD;DAT t SU;DAT HIGH t SU;STA t SU;STO Data t BUF P STOP S S START START t LOW = T73 t HD;STA = T80 t SU;STA = T81 t HIGH = T72 t HD;DAT = T78 t SU;STD = T82 tR = T74 t BUF tF = T75 t SU;DAT = T77 P STOP = T79 Figure 18.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 19. Example 3.3 VDC/SM_VCC Sequencing T0=95% 3.3 volt level Power Up 3.3 VDC/SM_VCC PWR_OK / OUTEN > T0 + 100ms VID_OUT T0 + 10mS VRM PWRGD > 10ms Processor PWRGOOD Processor RESET 1ms
Intel® Xeon™ Processor with 512 KB L2 Cache 3.0 Front Side Bus Signal Quality Specifications This section documents signal quality metrics used to derive topology and routing guidelines through simulation. All specifications are made at the processor core (pad measurements). Source synchronous data transfer requires the clean reception of data signals and their associated strobes.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 20. BCLK[1:0] Signal Integrity Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot 3.2 Front Side Bus Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in the appropriate platform design guidelines.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 23. Ringback Specifications for TAP Buffers Signal Group Transition Maximum Ringback (with Input Diodes Present) Threshold TAP and PWRGOO D L→H VT+(max) TO VT-(max) TAP and PWRGOO D H→L VT-(min) TO VT+(min) Notes Unit Figure VT+(max) V 23 1, 2, 3, 4, 5 VT-(min) V 24 1, 2, 3, 4, 5 NOTES: 1. All signal integrity specifications are measured at the processor core (pads). 2.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 22. High-to-Low Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers V CC +10% Vcc GTLREF Noise Margin -10% Vcc V SS Figure 23. Low-to-High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers Vcc Threshold Region to switch receiver to a logic 1. Vt+ (max) Vt+ (min) 0.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 24. High-to-Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Allowable Ringback Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min) Threshold Region to switch receiver to a logic 0.
Intel® Xeon™ Processor with 512 KB L2 Cache 3.3 Front Side Bus Signal Quality Specifications and Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The overshoot/undershoot specifications limit transitions beyond VCC or VSS due to the fast signal edge rates.
Intel® Xeon™ Processor with 512 KB L2 Cache 3.3.4 Activity Factor Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any common clock signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles.
Intel® Xeon™ Processor with 512 KB L2 Cache 3.3.6 Determining if a System Meets the Overshoot/Undershoot Specifications The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, AF and magnitude).
Intel® Xeon™ Processor with 512 KB L2 Cache Table 24. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.80 - 0.320 0.01 0.15 1.58 1.75 - 0.270 0.03 0.45 4.60 1.70 - 0.220 0.09 1.28 5.00 1.65 - 0.170 0.25 3.71 5.00 1.60 - 0.120 0.76 5.00 5.00 1.55 - 0.070 2.54 5.00 5.00 NOTES: 1.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 26. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.80 - 0.320 0.06 0.58 5.77 1.75 - 0.270 0.12 1.25 12.49 1.70 - 0.220 0.35 3.50 20.00 1.65 - 0.170 1.01 10.12 20.00 1.60 - 0.120 3.04 20.00 20.00 1.55 - 0.07 10.16 20.00 20.00 NOTES: 1.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 25.
Intel® Xeon™ Processor with 512 KB L2 Cache 56 Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache 4.0 Mechanical Specifications The Intel® Xeon™ processor with 512 KB L2 cache uses Interposer Micro Pin Grid Array (INTmPGA) package technology. Components of the package include a flip-chip ball grid array (FCBGA) package containing the processor die covered by an integrated heat spreader (IHS) mounted to a pinned FR4 interposer. Mechanical specifications for the processor are given in this section. See Section 1.1 for terminology definitions.
Intel® Xeon™ Processor with 512 KB L2 Cache 4.1 Mechanical Specifications Figure 27.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 28. INT-mPGA Processor Package Drawing Table 28. INT-mPGA Processor Package Dimensions Symbol A B C D E G H J K L M N φP Pin Tp Min 53.19 34.90 30.90 1.37 9.02 4.55 18.82 13.74 17.83 14.50 19.10 0.28 Milimeters Nominal 53.34 35.00 31.00 2.00 9.17 5.00 19.05 13.97 1.27 18.09 14.63 19.36 0.31 Notes Max 53.49 35.10 31.10 2.64 9.32 5.45 19.28 14.20 Nominal 18.34 14.76 19.61 0.36 0.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 29. INT-mPGA Processor Package Top View: Component Height Keep-in Figure 30 details the keep-in specification for pin-side components. The processor may contain pin side capacitors mounted to the processor package. These capacitors will be exposed within the opening of the interposer cavity. Figure 30. INT-mPGA Processor Package Cross Section View: Pin Side Component Keep-in IHS FCBGA Interposer 1.270mm 13.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 31. INT-mPGA Processor Package: Pin Detail 1. Kovar pin with plating of 0.2 micrometers Au over 2.0 micrometer Ni. 2. 0.254 Diametric true position, pin to pin.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 32 details the flatness and tilt specifications for the IHS of the Intel Xeon processor, respectively. Tilt is measured with the reference datum set to the bottom of the processor interposer. Figure 32. IHS Flatness and Tilt Drawing 4.2 Processor Package Load Specifications Table 29 provides dynamic and static load specifications for the processor IHS.
Intel® Xeon™ Processor with 512 KB L2 Cache 4.3 Insertion Specifications The processor can be inserted and removed 15 times from a 603-pin socket meeting the 603-Pin Socket Design Guidelines document. Note that this specification is based on design characterization and is not tested. 4.4 Mass Specifications Table 30 specifies the processors mass. This includes all components which make up the entire processor product. Table 30.
Intel® Xeon™ Processor with 512 KB L2 Cache 4.6 Markings The following section details the processor top-side laser markings. It is provided to aid in the identification of the processor. Figure 33. Processor Top-Side Markings INTEL CONFIDENTIAL i m c ‘00 {ATPO} NOTE: 1. Character size for laser markings is: height 0.050" (1.27mm), width 0.032" (0.81mm). 2. All characters will be in upper case. Processor Bottom-Side Markings 80528KC1.5G1M QXXXES {COO} {FPO}-[{SN} } Figure 34.
Intel® Xeon™ Processor with 512 KB L2 Cache 4.7 Pin-Out Diagram This section provides two view of the processor pin grid. Figure 35 and Figure 36 detail the coordinates of the processor pins. Figure 35.
Intel® Xeon™ Processor with 512 KB L2 Cache Processor Pin Out Diagram: Bottom View Async / JTAG 31 29 27 COMMON CLOCK 25 23 21 19 17 15 13 11 9 7 5 3 1 Vcc/Vss A B C D E F G H J K L M N P R T U V W Y AA AB AC A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AD AE 28 SMBus 26 24 22 20 18 16 14 12 10 DATA = Signal = Power = Ground 66 COMMON CLOCK ADDRESS Vcc/Vss Figure 36.
Intel® Xeon™ Processor with 512 KB L2 Cache 5.0 Pin Listing and Signal Definitions 5.1 Processor Pin Assignments Section 2.8 contains the front side bus signal groups in Table 4 for the Intel® Xeon™ processor with 512 KB L2 cache. This section provides a sorted pin list in Table 38 and Table 39. Table 38 is a listing of all processor pins ordered alphabetically by pin name. Table 39 is a listing of all processor pins ordered by pin number. 5.1.1 Pin Listing by Pin Name Table 38.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 38. Pin Listing by Pin Name Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 1 38. Pin Listing by Pin Name Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 38. Pin Listing by Pin Name Table 38. Pin Listing by Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VCC K7 VCC VCC VCC Table 38. Pin Listing by Pin Name Pin Name Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VCC V30 VCC W1 VCC 72 Table 38. Pin Listing by Pin Name Pin Name Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VSS E15 VSS VSS Table 38. Pin Listing by Pin Name Pin Name Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VSS P23 VSS P25 VSS 74 Table 38. Pin Listing by Pin Name Pin Name Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VSS AE2 Power/Other VSS AE11 Power/Other VSS AE21 Power/Other VSS AE27 Power/Other VSSA AA5 Power/Other Datasheet Table 38. Pin Listing by Pin Name Direction Input Pin Name Pin No. Signal Buffer Type Direction VSSSENSE D26 Power/Other Output 1. These are “Reserved” pins on the Intel Xeon processor.
Intel® Xeon™ Processor with 512 KB L2 Cache 5.1.2 Pin Listing by Pin Number Table 39. Pin Listing by Pin Number Table 39. Pin Listing by Pin Number Pin No. 76 Pin Name Signal Buffer Type A1 Reserved Reserved A2 VCC Power/Other A3 SKTOCC# Power/Other Direction Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type C4 VCC Power/Other C5 Reserved Reserved C6 RSP# Common Clk C7 VSS Power/Other C8 A35# Source Sync C9 A34# Source Sync C10 VCC Power/Other Table 39. Pin Listing by Pin Number Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 39. Pin Listing by Pin Number Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type H30 VSS H31 J1 J2 Table 39. Pin Listing by Pin Number Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type N5 VCC Power/Other 80 Direction Table 39. Pin Listing by Pin Number Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type U24 VSS U25 U26 U27 Table 39. Pin Listing by Pin Number Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type AA4 VCC Power/Other AA5 VSSA Power/Other AA6 VCC Power/Other AA7 TESTHI4 Power/Other AA8 D61# Source Sync AA9 VSS Power/Other AA10 D54# Source Sync 82 Table 39. Pin Listing by Pin Number Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 39. Pin Listing by Pin Number Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction Pin No.
Intel® Xeon™ Processor with 512 KB L2 Cache 5.2 Signal Definitions Table 41. Signal Definitions (Page 1 of 10) Name Type Description Notes I/O A[35:3]# (Address) define a 236 byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In subphase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the front side bus. A[35:3]# are protected by parity signals AP[1:0]#.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 2 of 10) Name BINIT# BNR# BPM[5:0]# BPRI# Datasheet Type Description I/O BINIT# (Bus Initialization) may be observed and driven by all processor front side bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 3 of 10) Name Type Description Notes BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. BR2# and BR3# must not be utilized in a dual processor platform design. The table below gives the rotating interconnect between the processor and bus signals for dual processor systems.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 4 of 10) Name Type Description Notes D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor front side bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 5 of 10) Name Type Description FERR#/PBE# O FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 6 of 10) Name LINT[1:0] LOCK# MCERR# ODTEN PROCHOT# Datasheet Type Description I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side bus agents. When the APIC functionality is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 7 of 10) Name Type Description I PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 8 of 10) Name Type Description SM_CLK I/O The SM_CLK (SMBus Clock) signal is an input clock to the system management logic which is required for operation of the system management features of the processor. This clock is driven by the SMBus controller and is asynchronous to other clocks in the processor. The processor includes a 10 KΩ pull-up resistor to SM_VCC for this signal.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 9 of 10) Name Type Description I All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor which matches the trace impedance within a range of ±10 ohms. TESTHI[3:0] and TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if desired. However, utilization of boundary scan test will not be functional if these pins are connected together.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 41. Signal Definitions (Page 10 of 10) Name Type Description VID[4:0] O VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages (VCC). Unlike previous processor generations, these pins are driven by processor logic. Hence the voltage supply for these pins (SM_VCC) must be valid before the VRM supplying Vcc to the processor is enabled.
Intel® Xeon™ Processor with 512 KB L2 Cache 94 Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache 6.0 Thermal Specifications This chapter provides the thermal specifications necessary for designing a thermal solution for the Intel® Xeon™ processor with 512 KB L2 cache. Thermal solutions should include heatsinks that attach to the integrated heat spreader (IHS). The IHS provides a common interface intended to be compatible with many heatsink designs.
Intel® Xeon™ Processor with 512 KB L2 Cache 6.1 Thermal Specifications Table 42 specifies the thermal design power dissipation envelope for the Intel® Xeon™ processor with 512 KB L2 cache. The processor power listed in Table 42 is described in thermal design power. Analysis indicates that real applications are unlikely to cause the processor to consume the maximum possible power consumption. Intel recommends that system thermal designs utilize the Thermal Design Power indicated in Table 42.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 39. Processor Thermal Design Power vs Electrical Projections for VID = 1.
Intel® Xeon™ Processor with 512 KB L2 Cache 6.2 Measurements for Thermal Specifications 6.2.1 Processor Case Temperature Measurement The minimum and maximum case temperatures (TCASE) for processors are specified in Table 42 of the previous section. These temperature specifications are meant to ensure correct and reliable operation of the processor. Figure 40 illustrates the thermal measurement point for TCASE. This point is at the geometric center of the integrated heat spreader (IHS). Figure 40.
Intel® Xeon™ Processor with 512 KB L2 Cache 7.0 Features 7.1 Power-On Configuration Options The Intel® Xeon™ processor with 512 KB L2 cache has several configuration options that are determined by the state of specific processor pins at the active-to-inactive transition of the processor RESET# signal. These configuration options cannot be changed except by another reset. Both power on and software induced resets reconfigure the processor(s). Table 43.
Intel® Xeon™ Processor with 512 KB L2 Cache 7.2.2 AutoHALT Powerdown State—State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front side bus. RESET# will cause the processor to immediately initialize itself.
Intel® Xeon™ Processor with 512 KB L2 Cache 7.2.3 Stop-Grant State—State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state.
Intel® Xeon™ Processor with 512 KB L2 Cache In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the front side bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
Intel® Xeon™ Processor with 512 KB L2 Cache For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers or interrupt handling routines. The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor Control Register is written to a “1” the TCC will be activated immediately, independent of the processor temperature.
Intel® Xeon™ Processor with 512 KB L2 Cache Note: The SMBus thermal sensor and its associated thermal diode are not related to, and are completely independent of, the precision on-die temperature sensor and thermal control circuit (TCC) of the Thermal Monitor feature discussed in Section 7.3. The processor SMBus implementation uses the clock and data signals of the V1.1 System Management Bus Specification. It does not implement the SMBSUS# signal.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 44.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 44.
Intel® Xeon™ Processor with 512 KB L2 Cache 7.4.2 Scratch EEPROM Also available in the memory component on the processor SMBus is an EEPROM which may be used for other data at the system or processor vendor’s discretion. The data in this EEPROM, once programmed, can be write-protected by asserting the active-high SM_WP signal. This signal has a weak pull-down (10 kW) to allow the EEPROM to be programmed in systems with no implementation of this signal.
Intel® Xeon™ Processor with 512 KB L2 Cache reading) is stored. These circuits compare the single byte result against programmable threshold bytes. If enabled, the alert signal on the processor SMBus (SM_ALERT#) will be asserted when the sensor detects that either threshold is reached or crossed. Analysis of SMBus thermal sensor data may be useful in detecting changes in the system environment that may require attention.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 49. Send Byte SMBus PacketReceive Byte SMBus Packet S Slave Address Read Ack Command Code Ack P 1 7-bits 1 1 8-bits 1 1 S Slave Address Read Ack Data /// P 1 7-bits 1 1 8-bits 1 1 Table 50. ARA SMBus Packet S ARA Read Ack Address /// P 1 0001 100 1 1 Device Address1 1 1 NOTE: 1. This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in the seven most significant bits.
Intel® Xeon™ Processor with 512 KB L2 Cache All of the commands in Table 51 are for reading or writing registers in the SMBus thermal sensor, except the one-shot command (OSHT) register. The one-shot command forces the immediate start of a new conversion cycle. If a conversion is in progress when the one-shot command is received, then the command is ignored. If the thermal sensor is in stand-by mode when the one-shot command is received, a conversion is performed and the sensor returns to stand-by mode.
Intel® Xeon™ Processor with 512 KB L2 Cache 7.4.6.3 Status Register The Status Register shown in Table 53 indicates which (if any) thermal value thresholds for the processor core thermal diode have been exceeded. It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection. Once set, alarm bits stay set until they are cleared by a Status Register read.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 54. SMBus Thermal Sensor Configuration Register Bit 7 (MSB) 7.4.6.5 Name Reset State Function 0 Mask SM_ALERT# bit. Clear bit to allow interrupts via SM_ALERT# and allow the thermal sensor to respond to the ARA command when an alarm is active. Set the bit to disable interrupt mode. The bit is not used to clear the state of the SM_ALERT# output. An ARA command may not be recognized if the mask is enabled. 0 Stand-by mode control bit.
Intel® Xeon™ Processor with 512 KB L2 Cache be cleared once the SMBus master device first reads the status register then reads the slave ARA unless the fault condition persists. Reading the Status Register alone or setting the mask bit within the Configuration Register does not clear the interrupt. 7.4.8 SMBus Device Addressing Of the addresses broadcast across the SMBus, the memory component claims those of the form “1010XXXZb”.
Intel® Xeon™ Processor with 512 KB L2 Cache Table 56. Thermal Sensor SMBus Addressing Address (Hex) Upper Address1 3Xh Device Select SM_TS_A1 SM_TS_A0 b[7:0] 0011 5Xh 0 0 0011000Xb Z2 0 0011001Xb 1 0 0011010Xb 0 Z2 0101001Xb Z Z 2 0101010Xb 1 Z2 0101011Xb 2 0101 9Xh 8-bit Address Word on Serial Bus 1001 0 1 1001100Xb Z2 1 1001101Xb 1 1 1001110Xb NOTES: 1. Upper address bits are decoded in conjunction with the select pins. 2.
Intel® Xeon™ Processor with 512 KB L2 Cache 8.0 Boxed Processor Specifications 8.1 Introduction The Intel® Xeon™ processor with 512 KB L2 cache is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The boxed processor is supplied with an unattached passive heatsink.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 44. Mechanical Representation of the Boxed Processor Passive Heatsink for 2 - 2.80 GHz processors 8.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor passive heatsink and the PWT. Proper clearance is required around the heatsink to ensure proper installation of the processor and unimpeded airflow for proper cooling. 8.2.
Intel® Xeon™ Processor with 512 KB L2 Cache 8.2.3 Retention Mechanism and Heatsink Supports The boxed processor requires processor retention solution to secure the processor, the baseboard, and the chassis. The retention solution contains one retention mechanisms and two retention clips per processor. The boxed processor ships with retention mechanism, cooling solution retention clips, and direct chassis attach screws.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 45.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 46.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 47.
Intel® Xeon™ Processor with 512 KB L2 Cache 8.2.4 Processor Wind Tunnel The boxed processor ships with an active duct cooling solution called the Processor Wind Tunnel, or PWT. This is an optional cooling solution that is designed to meet the thermal requirements of a diverse combination of baseboards and chassis. It ships with the processor in order to reduce the burden on the chassis manufacture to provide adequate airflow across the processor heatsink.
Intel® Xeon™ Processor with 512 KB L2 Cache . Table 58. Fan Cable Connector Requirements Item Specification Fan connector must be a straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. − Match with a straight pin, friction lock header on the mainboard. − Manufacturer and part number or equivalent: † o AMP : Fan connector: 643815-3, header: 640456-3 † † o Walden / Molex : Fan connector: 22-01-3037, header: 22-23-2031 − Pin 1: Ground; black wire.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 49.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 50.
Intel® Xeon™ Processor with 512 KB L2 Cache 8.3 1U Rack Mount Server Solution The 1U solution contains a passive heatsink and a foam pad, in addition to the retention solution included with the other options. Because of the small form factor, the 1U heatsink is not as efficient at dissipating heat as the general-purpose heatsink. In order to ensure maximum thermal efficiency, the foam pad must be attached to the top of the 1U heatsink, blocking airflow between the heatsink and the chassis cover.
Intel® Xeon™ Processor with 512 KB L2 Cache Figure 52.
Intel® Xeon™ Processor with 512 KB L2 Cache 8.4 Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor. 8.4.1 Boxed Processor Cooling Requirements The boxed processor will be directly cooled with a passive heatsink. For the passive heatsink to effectively cool the boxed processor, it is critical that sufficient, unimpeded, cool air flow over the heatsink of every processor in the system.
Intel® Xeon™ Processor with 512 KB L2 Cache 9.0 Debug Tools Specifications The Debug Port design information has been moved. This includes all information necessary to develop a Debug Port on this platform, including electrical specifications, mechanical requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700 Debug Port Design Guide for the design of your platform. 9.
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