Users Manual
Table Of Contents
- 2Functional Overview
- 3Interfaces Description
- 3.1Interfaces Parameter Definitions
- 3.2Interfaces Detail Description
- 3.2.1Power Supply Interface
- 3.2.2Touchscreen Interface
- 3.2.3Display Interface
- 3.2.4Camera Interfaces
- 3.2.5Audio Interface
- 3.2.6USB & DisplayPort Interface
- 3.2.7 PCIe Interface
- 3.2.8 SSC Interface
- 3.2.9 SDIO Interface
- 3.2.10 QUP Interface
- 3.2.11Power on Interface
- 3.2.12Reset Interface
- 3.2.13 Keys Interface
- 3.2.14 Sensor Interrupt Interface
- 3.2.15Debug UART Interface
- 3.2.16Battery Interface
- 3.2.17ADCs Interface
- 3.2.18 PWMs and LED Current Driver Interface
- 3.2.19Antenna Interface
- 4Connector PIN Summary
- 5Electrical Characteristics
Thundercomm TurboX D845 System on Module
Copyright © 2018 All Rights Reserved , Thundercomm Technology Co., Ltd.
23
3.2.8 SSC Interface
The SOM has an integrated sensor subsystem called Snapdragon™ sensor core (SSC), which is dedicated to
support low-power, always-on use cases.
The sensor subsystem can be left powered on even when the rest of the MSM device is in sleep mode. The
SSC has a dedicated 1.0MB L2/TCM cache.
The SSC core has dedicated I/O to communicate with the sensors. The I/O scan support I2C and SPI
interfaces.
SSC Interface
PIN Name Location PIN Voltage Type Description Notes
SSC_I2C1_SDA CON2402 7
PX12
OD
These I2C signals are
dedicated to Sensor
SSC_I2C1_SCL CON2402 9
PX12
OD
SSC_SPI1_MISO CON2401 149
PX12
DI
Snapdragon™ Sensor Core
SPI signals
SSC_SPI1_MOSI CON2401 151
PX12
DO
SSC_SPI1_CLK CON2401 153
PX12
DO
SSC_MAG_CS_L CON2401 135
PX12
DO
SSC_GYRO_CS_L CON2401 137
PX12
DO
SSC_ACCEL_CS_L CON2401 139
PX12
DO
SSC_SPI2_CS_L CON2401 142
PX12
DO
Snapdragon™ Sensor Core
SPI signals
SSC_SPI2_MOSI CON2401 144
PX12
DO
PCIE_0_CLK_REQ CON2401 6 PX3 DI
PCIe clock require signal,
need to reserve pull up
resistor
PCIE_0_RST_N CON2401 2 PX3 DO PCIe reset signal
PCIE_0_WAKE_N CON2401 4 PX3 DI PCIe wake up signal
PCIE1_REFCLK_P CON2401 122 AO
PCIe Signals
Compliant with PCI
Express Specification
Revision 3.0
PCIE1_REFCLK_M CON2401 124 AO
PCIE1_RX_P CON2401 116 AI
PCIE1_RX_M CON2401 118 AI
PCIE1_TX_M CON2401 128 AO
PCIE1_TX_P CON2401 130 AO
PCIE_1_CLK_REQ CON2401 110 PX3 DI
PCIe clock require signal,
need to reserve pull up
resistor
PCIE_1_RST_N CON2401 108 PX3 DO PCIe reset signal
PCIE_1_WAKE_N CON2401 112 PX3 DI PCIe wake up signal
Table 3.2- 7 PCIe interface definition