Users Manual

Thundercomm TurboX C865 System on Module
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Table 4.11-1 I2S
Figure 4.11-1 I2S timing diagram
The word-select signal is a 50% duty cycle signal Data is delayed 1 bit-clock, relative to the word select.
Data outputs are launched on the falling edge of the clock, and inputs data are captured on the rising edge of
the clock by the receiver.
I2S samples are 2’s complement values, and the MSB is transmitted first allowing the transmitter and receiver
to support different number of bits per sample.
The left channel is transmitted when the word select is low, and the right channel is transmitted when the
word select is high
Parameter
Comments
Min Typ Max Unit
Using internalSCK