Users Manual

Thundercomm TurboX C865 System on Module
Copyright © 2018 All Rights Reserved, Thundercomm Technology Co., Ltd.
18
2.2.8 SSC Interface
The SOM has an integrated sensor subsystem called Snapdragon™ sensor core (SSC), which is dedicated to
support low-power, always-on use cases.
The sensor subsystem can be left powered on even when the rest of the MSM device is in sleep mode. The
SSC has a dedicated 1.5MB L2/TCM cache.
The SSC core has dedicated I/O to communicate with the sensors. The I/O scan support I2C and SPI
interfaces.
SSC Interface
PIN Name Location PIN Voltage Type Description Notes
SNS_I2C0_SDA CON1 J37
P3
IO
These I2C signals are
dedicated to Sensor
GPIO160
SNS_I2C0_SCL CON1 H37
P3
IO GPIO161
SNS_I2C4_SDA CON1 H38
P3
IO
These I2C signals are
dedicated to Sensor
GPIO170
SNS_I2C4_SCL CON1 H39
P3
IO GPIO171
SPI2_MISO_IMU CON1 J40
P3
IO
Snapdragon™ Sensor
Core SPI signals
GPIO164
SPI2_MOSI_IMU CON1 J41
P3
IO GPIO165
SPI2_CLK_IMU CON1 J38
P3
IO GPIO166
SPI2_CS_IMU CON1 J39
P3
IO GPIO167
Table 3.2-8 SSC interface definition
PCIE1_TX1_M CON1 E14 AO
PCIE1_TX1_P CON1 F14 AO
GPIO_83 CON1 G39 DI PCIE Clock request
GPIO_82 CON1 G37 DO PCIe reset signal
GPIO_84 CON1 G38 DI PCIe wake up signal
PCIE2_REFCLK_M_MDM CON1 J21 AO
PCIe Signals
Compliant with PCI
Express Specification
Revision 3.0
PCIE2_REFCLK_P_MDM CON1 H21 AO
PCIE2_RX0_M_MDM CON1 J23 AI
PCIE2_RX0_P_MDM CON1 H23 AI
PCIE2_RX1_M_MDM CON1 K22 AI
PCIE2_RX1_P_MDM CON1 J22 AI
PCIE2_TX0_M_MDM CON1 K24 AI
PCIE2_TX0_P_MDM CON1 J24 AI
PCIE2_TX1_M_MDM CON1 J25 AO
PCIE2_TX1_P_MDM CON1 H25 AO
GPIO_86 CON1 D39 DI PCIe clock require
GPIO_85 CON1 F39 DO PCIe reset signal
Table 2.2-4 PCIe interface definition