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4.18 MMC FIFO Control Register (MMCFIFOCTL)
Registers
The MMC FIFO control register (MMCFIFOCTL) is shown in Figure 39 and described in Table 25 .
Figure 39. MMC FIFO Control Register (MMCFIFOCTL)
31 16
Reserved
R-0
15 5 4 3 2 1 0
Reserved ACCWD FIFOLEV FIFODIR FIFORST
R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 25. MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reserved
4-3 ACCWD 0-3h Access width. Used by FIFO control to determine full/empty flag.
0 CPU/EDMA access width of 4 bytes
1h CPU/EDMA access width of 3 bytes
2h CPU/EDMA access width of 2 bytes
3h CPU/EDMA access width of 1 byte
2 FIFOLEV FIFO level. Sets the threshold level that determines when the EDMA request and the FIFO threshold
interrupt are triggered.
0 EDMA request every 128 bits sent/received.
1 EDMA request every 256 bits sent/received.
1 FIFODIR FIFO direction. Determines if the FIFO is being written to or read from.
0 Read from FIFO.
1 Write to FIFO.
0 FIFORST FIFO reset. Resets the internal state of the FIFO.
0 FIFO reset is disabled.
1 FIFO reset is enabled.
Multimedia Card (MMC)/Secure Digital (SD) Card Controller58 SPRUE30B – September 2006
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