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6.7.1 Peripheral Revision and Class Information Register (PID)
6.7.2 Interrupt Evaluation Register (INTEVAL)
PSC Registers
The peripheral revision and class information (PID) register is shown in Figure 6-2 and described in
Table 6-6 .
Figure 6-2. Peripheral Revision and Class Information Register (PID)
31 30 29 28 27 16
SCHEME Reserved FUNC
R-1 R-0 R-482h
15 11 10 8 7 6 5 0
RTL MAJOR CUSTOM MINOR
R-4h R-1 R-0 R-5h
LEGEND: R = Read only; - n = value after reset
Table 6-6. Peripheral Revision and Class Information Register (PID) Field Descriptions
Bit Field Value Description
31-30 SCHEME 0-3h Distinguishes between the old scheme and the current scheme. There is a spare bit to encode future
schemes.
29-28 Reserved 0 Reserved
27-16 FUNC 0-FFFh Indicates a software compatible module family.
15-11 RTL RTL version.
4h Current RTL version.
10-8 MAJOR Major revision.
1h Current major revision.
7-6 CUSTOM 0-3h Indicates a special version for a particular device.
5-0 MINOR Minor revision.
5h Current minor revision.
The interrupt evaluation register (INTEVAL) is shown in Figure 6-3 and described in Table 6-7 .
Figure 6-3. Interrupt Evaluation Register (INTEVAL)
31 16
Reserved
R-0
15 1 0
Reserved ALLEV
R-0 W-0
LEGEND: R = Read only; W= Write only; - n = value after reset
Table 6-7. Interrupt Evaluation Register (INTEVAL) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 ALLEV Evaluate PSC interrupt.
0 A write of 0 has no effect.
1 A write of 1 re-evaluates the interrupt condition.
SPRU978E – March 2008 Power and Sleep Controller 69
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