TMS320C6747 DSP Universal Serial Bus (USB) OHCI Host Controller User's Guide Literature Number: SPRUFM8 September 2008
SPRUFM8 – September 2008 Submit Documentation Feedback
Contents Preface ........................................................................................................................................ 6 1 Introduction......................................................................................................................... 7 1.1 2 3 Purpose of the Peripheral ................................................................................................ 7 .................................................................................
www.ti.com List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 4 Relationships Between Virtual Address Physical Address............................................................ OHCI Revision Number Register (HCREVISION) ..................................................................... HC Operating Mode Register (HCCONTROL) ......................................................................... HC Command and Status Register (HCCOMMANDSTATUS) ...........................
www.ti.com List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 USB Host Controller Registers ........................................................................................... OHCI Revision Number Register (HCREVISION) Field Descriptions ............................................... HC Operating Mode Register (HCCONTROL) Field Descriptions ................................................... HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions ...........
Preface SPRUFM8 – September 2008 Read This First About This Manual This document describes the universal serial bus OHCI host controller. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register.
User's Guide SPRUFM8 – September 2008 Universal Serial Bus OHCI Host Controller 1 Introduction This document describes the universal serial bus OHCI host controller. 1.1 Purpose of the Peripheral The USB OHCI host controller (HC) is a single port controller that communicates with USB devices at the USB low-speed (1.5M bit-per-second maximum) and full-speed (12M bit-per-second maximum) data rates. It is compatible with the Universal Serial Bus Specification Revision 2.
Architecture 2 Architecture 2.1 USB1 Module Clock and Reset www.ti.com The USB1 module requires that several different clocks are present before it can be accessed: 1. Internal system bus clocks for accesses by the ARM or DSP (Device SYSCLK2 and SYSCLK4) 2. Local bus clock to the USB Host controller (derived from SYSCLK4) 3. USB bus side 48-MHz reference clock must be present. Several options are available to source this clock. 2.1.
Architecture www.ti.com 2.2 2.2.1 USB1 Module Open Host Controller Interface Functionality OHCI Controller Overview The Open HCI—Open Host Controller Interface Specification for USB, Release 1.0a defines a set of registers and data structures stored in system memory that control how a USB host controller interfaces to system software. This specification, in conjunction with the Universal Serial Bus Specification Version 2.0, defines most of the USB functionality that the USB host controller provides.
Architecture 2.4 2.4.1 www.ti.com Implementation of OHCI Specification for USB USB Host Controller Endpoint Descriptor (ED) List Head Pointers The OHCI Specification for USB provides a specific sequence of operations for the host controller driver to perform when setting up the host controller. Failure to follow that sequence can result in malfunction.
Architecture www.ti.com 2.5 OHCI Interrupts The USB1 host controller can be controlled either by the ARM or the DSP. It has the ability to interrupt either processor. 2.6 USB Host Controller Access to System Memory The USB1 module needs to access system memory to read and write the OHCI data structures and data buffers associated with USB traffic. The switch fabric allows the USB host controller to access system memory, as shown in . 2.
Registers 3 www.ti.com Registers Most of the host controller (HC) registers are OHCI operational registers, defined by the OHCI Specification for USB. Four additional registers not specified by the OHCI Specification for USB provide additional information about the USB host controller state. USB host controller registers can be accessed in user and supervisor modes.
Registers www.ti.com 3.1 OHCI Revision Number Register (HCREVISION) The OHCI revision number register (HCREVISION) is shown in Figure 2 and described in Table 2. Figure 2. OHCI Revision Number Register (HCREVISION) 31 16 Reserved R-0 15 8 7 0 Reserved REV R-0 R-10h LEGEND: R = Read only; -n = value after reset Table 2. OHCI Revision Number Register (HCREVISION) Field Descriptions Bit Field Value 31-8 Reserved 7-0 REV 3.2 0 10h Description Reserved OHCI revision number.
Registers www.ti.com Table 3. HC Operating Mode Register (HCCONTROL) Field Descriptions Bit 31-11 Reserved Value 0 Description Reserved 10 RWE 0-1 Remote wake-up enable. 9 RWC 0-1 Remote wake-up connected. 8 IR 7-6 5 4 3 2 1-0 14 Field HCFS 0 0-3h Host controller functional state. A transition to USB operational causes SOF generation to begin in 1 ms. The USB host controller can automatically transition from USB suspend to USB resume, if a downstream resume is received.
Registers www.ti.com 3.3 HC Command and Status Register (HCCOMMANDSTATUS) The HC command and status register (HCCOMMANDSTATUS) shows the current state of the host controller and accepts commands from the host controller driver. HCCOMMANDSTATUS is shown in Figure 4 and described in Table 4. Figure 4.
Registers 3.4 www.ti.com HC Interrupt and Status Register (HCINTERRUPTSTATUS) The HC interrupt and status register (HCINTERRUPTSTATUS) reports the status of the USB host controller internal interrupt sources. HCINTERRUPTSTATUS is shown in Figure 5 and described in Table 5. Figure 5.
Registers www.ti.com 3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) The HC interrupt enable register (HCINTERRUPTENABLE) enables various OHCI interrupt sources to generate interrupts to the level 2 interrupt controller. HCINTERRUPTENABLE is shown in Figure 6 and described in Table 6. Figure 6.
Registers 3.6 www.ti.com HC Interrupt Disable Register (HCINTERRUPTDISABLE) The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interrupt enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in Figure 7 and described in Table 7. Figure 7.
Registers www.ti.com 3.7 HC HCAA Address Register (HCHCCA) The HC HCAA address register (HCHCCA) defines the physical address of the beginning of the HCCA. HCHCCA is shown in Figure 8 and described in Table 8. Figure 8. HC HCAA Address Register (HCHCCA) 31 16 HCCA R/W-0 15 8 7 0 HCCA Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8. HC HCAA Address Register (HCHCCA) Field Descriptions Bit Field Value 31-8 HCCA 0-FF FFFFh 7-0 Reserved 3.
Registers 3.9 www.ti.com HC Head Control Register (HCCONTROLHEADED) The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpoint descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in Figure 10 and described in Table 10. Figure 10. HC Head Control Register (HCCONTROLHEADED) 31 16 CHED R/W-0 15 4 3 0 CHED Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10.
Registers www.ti.com 3.10 HC Current Control Register (HCCONTROLCURRENTED) The HC current control register (HCCONTROLCURRENTED) defines the physical address of the next endpoint descriptor (ED) on the control ED list. HCCONTROLCURRENTED is shown in Figure 11 and described in Table 11. Figure 11. HC Current Control Register (HCCONTROLCURRENTED) 31 16 CCED R/W-0 15 4 3 0 CCED Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11.
Registers www.ti.com 3.11 HC Head Bulk Register (HCBULKHEADED) The HC head bulk register (HCBULKHEADED) defines the physical address of the head endpoint descriptor (ED) on the bulk ED list. HCBULKHEADED is shown in Figure 12 and described in Table 12. Figure 12. HC Head Bulk Register (HCBULKHEADED) 31 16 BHED R/W-0 15 4 3 0 BHED Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 12.
Registers www.ti.com 3.13 HC Head Done Register (HCDONEHEAD) The HC head done register (HCDONEHEAD) defines the physical address of the current head of the done TD queue. HCDONEHEAD is shown in Figure 14 and described in Table 14. Figure 14. HC Head Done Register (HCDONEHEAD) 31 16 DH R-0 15 4 3 0 DH Reserved R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 14.
Registers www.ti.com 3.15 HC Frame Remaining Register (HCFMREMAINING) The HC frame remaining register (HCFMREMAINING) reports the number of full-speed bit times remaining in the current frame. HCFMREMAINING is shown in Figure 16 and described in Table 16. Figure 16. HC Frame Remaining Register (HCFMREMAINING) 31 30 16 FRT Reserved R-0 R-0 15 14 13 0 Reserved FR R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 16.
Registers www.ti.com 3.17 HC Periodic Start Register (HCPERIODICSTART) The HC periodic start register (HCPERIODICSTART) defines the position within the USB frame where endpoint descriptors (EDs) on the periodic list have priority over EDs on the bulk and control lists. HCPERIODICSTART is shown in Figure 18 and described in Table 18. Figure 18.
Registers www.ti.com 3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD) The HC low-speed threshold register (HCLSTHRESHOLD) defines the latest time in a frame that the USB host controller can begin a low-speed packet. HCLSTHRESHOLD is shown in Figure 19 and described in Table 19. Figure 19. HC Low-Speed Threshold Register (HCLSTHRESHOLD) 31 16 Reserved R-0 15 14 13 0 Reserved LST R-0 R/W-628h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19.
Registers www.ti.com 3.19 HC Root Hub A Register (HCRHDESCRIPTORA) The HC root hub A register (HCRHDESCRIPTORA) defines several aspects of the USB host controller root hub functionality. HCRHDESCRIPTORA is shown in Figure 20 and described in Table 20. Figure 20.
Registers www.ti.com 3.20 HC Root Hub B Register (HCRHDESCRIPTORB) The HC root hub B register (HCRHDESCRIPTORB) defines several aspects of the USB host controller root hub functionality. HCRHDESCRIPTORB is shown in Figure 21 and described in Table 21. Note: The device does not provide connections from the USB host controller to pins to provide external port power switching. Systems that implement port power switching must use other mechanisms to control port power. Figure 21.
Registers www.ti.com 3.21 HC Root Hub Status Register (HCRHSTATUS) The HC root hub status register (HCRHSTATUS) reports the USB host controller root hub status. HCRHSTATUS is shown in Figure 22 and described in Table 22. Figure 22. HC Root Hub Status Register (HCRHSTATUS) 17 16 CRWE 31 Reserved OCIC LPSC R/W-0 R-0 R/W-0 R/W-0 15 30 18 1 0 DRWE 14 Reserved 2 OCI LPS R/W-0 R-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22.
Registers www.ti.com 3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) The HC port 1 status and control register (HCRHPORTSTATUS1) reports and controls the state of USB host port 1. HCRHPORTSTATUS1 is shown in Figure 23 and described in Table 23. Figure 23.
Registers www.ti.com Table 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions (continued) Bit 8 Field 7-5 Reserved 4 PRS/SPR 3 2 1 0 Value PPS/SPP Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set the port 1 port power status bit; a write of 0 has no effect.
Registers www.ti.com 3.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) The HC port 2 status and control register (HCRHPORTSTATUS2) reports and controls the state of USB host port 2. HCRHPORTSTATUS2 is shown in Figure 24 and described in Table 24. Figure 24.
Registers www.ti.com Table 24. HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions (continued) Bit 8 Field 7-5 Reserved 4 PRS/SPR 3 2 1 0 Value PPS/SPP Port 2 port power status/set port power. This bit indicates, when read as 1, that the port 2 power is enabled. When read as 0, port 2 power is not enabled.
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