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5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
EMAC Port Registers
The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 44 and described in
Table 44 .
Figure 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
MASK MASK MASK MASK MASK MASK MASK MASK
R-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0
LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; - n = value after reset
Table 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 RX7MASK Receive channel 7 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
6 RX6MASK Receive channel 6 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
5 RX5MASK Receive channel 5 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
4 RX4MASK Receive channel 4 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
3 RX3MASK Receive channel 3 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
2 RX2MASK Receive channel 2 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
1 RX1MASK Receive channel 1 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0 RX0MASK Receive channel 0 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 99
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