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5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
EMAC Port Registers
The receive interrupt status (Unmasked) register (RXINTSTATRAW) is shown in Figure 41 and described
in Table 41 .
Figure 41. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
PEND PEND PEND PEND PEND PEND PEND PEND
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 41. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 RX7PEND RX7PEND raw interrupt read (before mask)
6 RX6PEND RX6PEND raw interrupt read (before mask)
5 RX5PEND RX5PEND raw interrupt read (before mask)
4 RX4PEND RX4PEND raw interrupt read (before mask)
3 RX3PEND RX3PEND raw interrupt read (before mask)
2 RX2PEND RX2PEND raw interrupt read (before mask)
1 RX1PEND RX1PEND raw interrupt read (before mask)
0 RX0PEND RX0PEND raw interrupt read (before mask)
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)96 SPRU975B – August 2006
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