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5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET)
EMAC Port Registers
The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 38 and described in
Table 38 .
Figure 38. Transmit Interrupt Mask Set Register (TXINTMASKSET)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
MASK MASK MASK MASK MASK MASK MASK MASK
R-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 38. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 TX7MASK Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
6 TX6MASK Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
5 TX5MASK Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
4 TX4MASK Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
3 TX3MASK Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
2 TX2MASK Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
1 TX1MASK Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0 TX0MASK Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 93
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