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5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
EMAC Port Registers
The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 36 and described
in Table 36 .
Figure 36. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
PEND PEND PEND PEND PEND PEND PEND PEND
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 36. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 TX7PEND TX7PEND raw interrupt read (before mask)
6 TX6PEND TX6PEND raw interrupt read (before mask)
5 TX5PEND TX5PEND raw interrupt read (before mask)
4 TX4PEND TX4PEND raw interrupt read (before mask)
3 TX3PEND TX3PEND raw interrupt read (before mask)
2 TX2PEND TX2PEND raw interrupt read (before mask)
1 TX1PEND TX1PEND raw interrupt read (before mask)
0 TX0PEND TX0PEND raw interrupt read (before mask)
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 91
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