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5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
EMAC Port Registers
The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 46 and described
in Table 46 .
Figure 46. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
31 16
Reserved
R-0
15 2 1 0
Reserved HOST STAT
PEND PEND
R-0 R-0 R-0
LEGEND: R/W = R = Read only; - n = value after reset
Table 46. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTPEND Host pending interrupt (HOSTPEND); masked interrupt read
0 STATPEND Statistics pending interrupt (STATPEND); masked interrupt read
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 101
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