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5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
EMAC Port Registers
The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 45 and described
in Table 45 .
Figure 45. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
31 16
Reserved
R-0
15 2 1 0
Reserved HOST STAT
PEND PEND
R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 45. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTPEND Host pending interrupt (HOSTPEND); raw interrupt read (before mask)
0 STATPEND Statistics pending interrupt (STATPEND); raw interrupt read (before mask)
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)100 SPRU975B – August 2006
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