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V-

V+

V-

V+

100nF

1 Fm

100nF

10 Hm

XTR300

SBOS336C –JUNE 2005– REVISED JUNE 2011

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LAYOUT CONSIDERATIONS

Supply bypass capacitors should be close to the package and connected with low-impedance conductors. Avoid

noise coupled into R

GAIN

, and observe wiring resistance. For thermal management, see the Package and Heat

Sinking section.

Layout for the XTR300 is not critical; however, its internal current chopping works best with good (low dynamic

impedance) supply decoupling. Therefore, avoid throughhole contacts in the connection to the bypass capacitors

or use multiple through-hole contacts. Switching noise from chopper-type power supplies should be filtered

enough to reduce influence on the circuit. Small resistors (2Ω, for example) or damping inductors in series with

the supply connection (between the dc/dc converter and the XTR circuit) act as a decoupling filter together with

the bypass capacitor, as shown in Figure 48.

Resistors connected close to the input pins help dampen environmental noise coupled into conductor traces.

Therefore, place the OPA input- and IA input-related resistors close to the package. Also, avoid additional wire

resistance in series to R

SET

, R

, and R

GAIN

(observe the reliability of the through-hole contacts), because this

resistance could produce gain and offset error as well as drift; 1Ω is already 0.1% of the 1kΩ resistor.

The exposed lead-frame die pad on the bottom of the package must be connected to V−, pin 11 (see the QFN

Package and Heat Sinking section for more details).

Figure 48. Suggested Supply Decoupling for Noisy Chopper-Type Supplies

QFN PACKAGE AND HEAT SINKING

The XTR300 is available in a QFN package. This leadless, near-chip-scale package maximizes board space and

enhances thermal and electrical characteristics of the device through an exposed thermal pad.

Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but

printed circuit board (PCB) layout greatly influences overall heat dissipation. The thermal resistance from

junction-to-ambient (θ

) is specified for the packages with the exposed thermal pad soldered to a normalized

PCB, as described in Technical Brief SLMA002, PowerPAD™ Thermally-Enhanced Package. See also

EIA/JEDEC Specifications JESD51-0 to 7, QFN/SON PCB Attachment (SLUA271), and Quad Flatpack No-Lead

Logic Packages (SCBA017). These documents are available for download at www.ti.com.

NOTE: All thermal models have an accuracy variation of ±20%.

Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load

conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress

for proper long-term operation with a junction temperature well below +125°C.

The exposed lead-frame die pad on the bottom of the package must be connected to the V− pin.