Datasheet

XTR300
www.ti.com SBOS336C –JUNE 2005– REVISED JUNE 2011
DRIVING CAPACITIVE LOADS AND LOOP COMPENSATION
For normal operation, the driver OPA and the IA are connected in a closed loop for voltage output. In current
output mode, the current copy closes the loop directly.
In current output mode, loop compensation is not critical, even for large capacitive loads. However, in voltage
output mode, the capacitive load, together with the source impedance and the impedance of the protection
circuit, generates additional phase lag. The IA input might also be protected by a low-pass filter that influences
phase in the closed loop.
The loop compensation low-pass filter consists of C
C
and the parallel resistance of R
OS
and R
SET
. For loop
stability with large capacitive load, the external phase shift has to be added to the OPA phase. With C
C
, the
voltage gain of the OPA has to approach zero at the frequency where the total phase approaches 180° + 135°.
The best stability for large capacitive loads is provided by adding a small resistor, R
C
(15Ω). See the Output
Protection section.
An empirical method of evaluation is using a square wave input signal and observing the settling after transients.
Use small signal amplitudes only—steep signal edges cause excessive current to flow into the capacitive load
and may activate the current limit, which hides or prevents oscillation. A small-signal oscillation can be hidden
from large capacitive loads, but observing the I
MON
output on an appropriate resistor (use a similar value like
R
SET
||R
OS
) would indicate stability issues. Note that noise pulses at I
MON
during overload (EF
LD
active) are normal
and are caused by cycling of the current mirror.
The voltage output mode includes the IA in the loop. An additional low-pass filter in the input reverses the phase
and therefore increases the signal bandwidth of the loop, but also increases the delay. Again, loop stability has to
be observed. Overloading the IA disconnects the closed loop and the output voltage rails.
INTERNAL CURRENT SOURCES, SWITCHING NOISE, AND SETTLING TIME
The accuracy of the current output mode and the dc performance of the IA rely on dynamically-matched current
mirrors.
Identical current sources are rotated to average out mismatch errors. It can take several clock cycles of the
internal 100kHz oscillator (or a submultiple of that frequency) to reach full accuracy. This may dominate the
settling time to the 0.1% accuracy level and can be as much as 100μs in current output mode or 40μs in voltage
output mode.
A small portion of the switching glitches appear at the DRV output, and also at the I
MON
and IA
MON
outputs. The
standard circuit configuration, with R
C
, C
4
, and C
C
, which are required for loop compensation and output
protection, also helps reduce the noise to negligible levels at the signal output. If necessary, the monitor outputs
can be filtered with a shunt capacitor.
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