Datasheet

XTR117
SBOS344C − SEPTEMBER 2005 − REVISED MAY 2012
www.ti.com
8
A1
+5V
Regulator
Q1
E
B
V+
7
6
5
4
8
2
3
P
+125_ C
−40_ C
Ext Temp
Ext Temp
Nonlinear
Bridge
Transducer
Fault
Monitor
Int Temp
Te m p
ADC
Digital
Temperature
Compensation
Auto−Zero
PGA
Over/Under
Scale Limiter
Control Register
Interface Circuitry
EEPROM
(SOT23−5)
Digital Calibration
NOTE: (1) PGA309 V
OUT
: 0.5V to 4.5V.
50
0
psi
T
R
L
V
LOOP
I
O
V
REG
V
S
R
IN
25k
Ω
R
OS
125k
Ω
Linear
2.5V
Ref
Lin DAC
Linearization
Circuit
Analog Sensor Linearization
Analog Signal Conditioning
V
OUT
(1)
R
1
2.475k
Ω
R
2
25Ω
R
LIM
R
IN
I
O
=100V
IN
I
IN
I
RET
XTR117
PGA309
Figure 5. Complete 4-20mA Pressure Transducer Solution with PGA309 and XTR117
DFN PACKAGE
The XTR117 is offered in a DFN-8 package (also known
as SON). The DFN is a QFN package with lead contacts
on only two sides of the bottom of the package. This
leadless package maximizes board space and
enhances thermal and electrical characteristics through
an exposed pad.
DFN packages are physically small, have a smaller
routing area, improved thermal performance, and
improved electrical parasitics. Additionally, the absence
of external leads eliminates bent-lead issues.
The DFN package can be easily mounted using
standard printed circuit board (PCB) assembly
techniques. See Application Note, QFN/SON PCB
Attachment (SLUA271) and Application Report, Quad
Flatpack No-Lead Logic Packages (SCBA017), both
available for download at www.ti.com.
The exposed leadframe die pad on the bottom of
the package should be connected to I
RET
or left
unconnected.
LAYOUT GUIDELINES
The exposed leadframe die pad on the DFN package
should be soldered to a thermal pad on the PCB. A
mechanical drawing showing an example layout is
attached at the end of this data sheet. Refinements to
this layout may be required based on assembly process
requirements. Mechanical drawings located at the end
of this data sheet list the physical dimensions for the
package and pad. The five holes in the landing pattern
are optional, and are intended for use with thermal vias
that connect the leadframe die pad to the heatsink area
on the PCB.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests.
Even with applications that have low power dissipation,
the exposed pad must be soldered to the PCB to
provide structural integrity and long-term stability.