Datasheet

XTR111
www.ti.com SBOS375C –NOVEMBER 2006– REVISED JUNE 2011
PACKAGE AND HEAT SINKING NOTE: All thermal models have an accuracy variation
of 20%.
The dominant portion of power dissipation for the
current output is in the external FET. Component population, layout of traces, layers, and
air flow strongly influence heat dissipation.
The XTR111 only generates heat from the supply
Worst-case load conditions should be tested in the
voltage with the quiescent current, the internal signal
real environment to ensure proper thermal conditions.
current that is 1/10 of the output current, and the
Minimize thermal stress for proper long-term
current and internal voltage drop of the regulator.
operation with a junction temperature well below
+125°C.
The exposed thermal pad on the bottom of the
XTR111 package allows excellent heat dissipation of
the device into the printed circuit board (PCB). LAYOUT GUIDELINES
The leadframe die pad should be soldered to a
THERMAL PAD
thermal pad on the PCB. A mechanical data sheet
showing an example layout is attached at the end of
The thermal pad must be connected to the same
this data sheet. Refinements to this layout may be
voltage potential as the device GND pin.
required based on assembly process requirements.
Packages with an exposed thermal pad are
Mechanical drawings located at the end of this data
specifically designed to provide excellent power
sheet list the physical dimensions for the package
dissipation, but board layout greatly influences overall
and pad. The five holes in the landing pattern are
heat dissipation. The thermal resistance from
optional, and are intended for use with thermal vias
junction-to-ambient (T
JA
) is specified for the packages
that connect the leadframe die pad to the heatsink
with the exposed thermal pad soldered to a
area on the PCB.
normalized PCB, as described in Technical Brief
Soldering the exposed pad significantly improves
SLMA002, PowerPAD Thermally-Enhanced Package.
board-level reliability during temperature cycling, key
See also EIA/JEDEC Specifications JESD51-0 to 7,
push, package shear, and similar board-level tests.
QFN/SON PCB Attachment (SLUA271), and Quad
Even with applications that have low-power
Flatpack No-Lead Logic Packages (SCBA017).
dissipation, the exposed pad must be soldered to the
These documents are available for download at
PCB to provide structural integrity and long-term
www.ti.com.
reliability.
space
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June, 2010) to Revision C Page
• Corrected wiring error in Figure 46 ..................................................................................................................................... 19
Changes from Revision A (August, 2007) to Revision B Page
• Corrected errors in Figure 37 .............................................................................................................................................. 14
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