Datasheet

XTR108
14
SBOS187C
www.ti.com
Address = 4: Control Register 2
If the RBD bit is set to ‘1’, the automatic read-back from the
EEPROM will be disabled after a valid checksum byte is
received in Register 15. This bit is read from the EEPROM
during a read-back by the XTR108 and allows the user to
program the XTR108 to read the EEPROM data once
(instead of continuously), and then disables the automatic
read-back function. The XTR108 will continuously read the
EEPROM if RBD is set to ‘0’. The remaining bits in this
register must be set to ‘0’.
Address = 5: Over- and Under-Scale Register
This register sets the magnitude of the over-scale current
limit and the magnitude of the under-scale current limit. The
threshold level, as shown in Table VII and VIII, is the
normal analog (no error condition) output limit. If an input
voltage to the PGA exceeds the linear operation range, the
output will be programmed to either the over-scale error
level or the under-scale error level. The over-scale error
level is 10mA greater than the over-scale threshold level.
The under-scale error level is 0.4mA less than the under-
scale threshold level. The FD bit will disable the over-scale
and under-scale limiting function as well as the PGA fault
indication error levels.
Address = 6: PGA Gain Register
This register sets the gain of the programmable-gain ampli-
fier. The unused bits must always be set to ‘0’. The gain step
to register content is given in Table IX.
Address = 7: Alarm Configuration Register
This register configures whether the XTR108 will go over-
scale or under-scale for various detected fault conditions at
the input of the PGA. Table X defines each of the bits.
If a bit corresponding to the particular error is set to ‘1’, the
output will go over-scale when it occurs and if a bit corre-
sponding to the particular error is set to ‘0’, the output will
go under-scale.
Address = 8: PGA Input Configuration Register
This register connects the inputs of the PGA to the various
multiplexed input pins. Tables XI and XII show the relation-
ship between register, contents, and PGA inputs.
I
O
OVER-SCALE
V
O
OVER-SCALE THRESHOLD
OS3 OS2 OS1 OS0 THRESHOLD R
VI
= 6.34kΩ
0 0 0 0 2.625V 20.7mA
0 0 0 1 2.6875V 21.2mA
0 0 1 0 2.75V 21.7mA
0 0 1 1 2.8125V 22.2mA
0 1 0 0 2.875V 22.7mA
0 1 0 1 2.9375V 23.2mA
0 1 1 0 3.0V 23.7mA
0 1 1 1 3.0625V 24.2mA
1 0 0 0 3.125V 24.6mA
1 0 0 1 3.1875V 25.1mA
1 0 1 0 3.25V 25.6mA
1 0 1 1 3.3125V 26.1mA
1 1 0 0 3.375V 26.6mA
1 1 0 1 3.4375V 27.1mA
1 1 1 0 3.5V 27.6mA
1 1 1 1 3.5625V 28.1mA
TABLE VII. Register 5, Over-Scale Threshold.
I
O
UNDER-SCALE
V
O
UNDER-SCALE THRESHOLD
US2 US1 US0 THRESHOLD R
VI
= 6.34kΩ
0 0 0 450mV 3.55mA
0 0 1 425mV 3.35mA
0 1 0 400mV 3.15mA
0 1 1 375mV 2.96mA
1 0 0 350mV 2.76mA
1 0 1 325mV 2.56mA
1 1 0 300mV 2.37mA
1 1 1 275mV 2.17mA
TABLE VIII. Register 5, Under-Scale Threshold.
SIGNAL PATH
PGA TRANSCONDUCTANCE
G2 G1 G0 VOLTAGE GAIN R
VI
= 6.34kΩ
0 0 0 6.25V/V 49mA/V
0 0 1 12.5V/V 99mA/V
0 1 0 25V/V 197mA/V
0 1 1 50V/V 394mA/V
1 0 0 100V/V 789mA/V
1 0 1 200V/V 1577mA/V
1 1 0 400V/V 3155mA/V
1 1 1 Reserved
TABLE IX. Register 6, PGA Gains.
BITACACACACAC ACAC AC
# 76543 21 0
V
INN
hl lhnnl h
V
INP
lhlhl hnn
NOTES: ‘h’ = input exceeds positive common-mode range, ‘l’ = input exceeds
negative common-mode range, and ‘n’ = input pin is within the CM range.
TABLE X. Register 7, Alarm Configuration Register.
VP2 VP1 VP0 PGA POSITIVE INPUT
0 0 0 PGA V
IN+
Connected to V/ I-0
0 0 1 PGA V
IN+
Connected to V/ I-1
0 1 0 PGA V
IN+
Connected to V/ I-2
0 1 1 PGA V
IN+
Connected to V/ I-3
1 0 0 PGA V
IN+
Connected to V/I-4
1 0 1 PGA V
IN+
Connected to V/I-5
1 1 0 Reserved
1 1 1 Reserved
TABLE XI. Register 8, PGA Positive Input Selection.
VN2 VN1 VN0 PGA NEGATIVE INPUT
0 0 0 PGA V
IN–
Connected to V/I-0
0 0 1 PGA V
IN–
Connected to V/I-1
0 1 0 PGA V
IN–
Connected to V/I-2
0 1 1 PGA V
IN–
Connected to V/I-3
1 0 0 PGA V
IN–
Connected to V/I-4
1 0 1 PGA V
IN–
Connected to V/I-5
1 1 0 Reserved
1 1 1 Reserved
TABLE XII. Register 8, PGA Negative Input Selection.