Datasheet

XTR108
13
SBOS187C
www.ti.com
The uncommitted amplifier can be used for a variety of
purposes, such as voltage sensor excitation, buffering the
REF
OUT
pin, four-wire RTD connection, or sensing the
bridge voltage for temperature compensation.
POWER-GOOD/POWER-ON RESET
In case of a supply brownout condition or short interruption,
the XTR108 power-good detection circuit will initiate a chip
reset that will cause all registers to be reset to 0’s and a cycle
of EEPROM read to begin. The circuit generates a reset if
V
S
droops below 1.5V and then recovers up to the normal
level.
USING THE XTR108 IN VOLTAGE OUTPUT MODE
The XTR108 can be used not only in 4-20mA current loops,
but also as a low-power, single-supply, "smart" sensor-
conditioning chip with voltage output. In this mode,
the I
RET
pin must be connected below ground
(–200mV < I
RET
< –25mV). This negative voltage is
required to overcome the input offset voltage of the output
current amplifier and prevent it from turning on and drawing
excessive current. An application circuit that generates this
negative voltage using the XTR108 clock output and a
simple charge pump is shown in the application section.
The sub-regulator with an external MOSFET may or may not
be used. If the circuit is powered externally, the supply
voltage must be in the range of 5V ±0.5V.
CONTROL REGISTERS
Table V shows the registers that control the analog functions
of the XTR108.
DESCRIPTION OF CONTROL REGISTERS
Address = 0: Control Register 1
If the RST bit is set to ‘1’ in a write operation, all the
registers in the XTR108 will be returned to their power-on
reset condition. The RST bit will always read as a ‘0’. CSE,
the checksum error bit, is read only and will be set to ‘1’ if
a checksum error has been detected. This bit is cleared by a
reset operation or by detection of a valid checksum. The
remaining bits are reserved and must be set to ‘0’.
Address = 3: Fault Status Register
This register is a read-only register. If the input voltage to
the PGA exceeds the linear range of operation, the XTR108
will indicate this error condition (typically caused by a
sensor fault) by setting the under-scale or over-scale error
level depending on the state of the Alarm Configuration
Register (Address = 7). Information on the nature of the fault
may be read in digital form from this register, as shown in
Table VI. The remaining bits will be set to ‘0’.
TABLE V. Analog Control Registers.
Instruction D7 D6 D5 D4 D3 D2 D1 D0
Read/Write R/W 0 0 0 A3 A2 A1 A0
EEPROM Mode 0 1 1 1 1111
D7 D6 D5 D4 D3 D2 D1 D0
0 RST CSE 0 0 0 0 0 0 Read/Write Control Register 1
100000000Reserved
200000000Reserved
30000F3F2F1F0Read Only Fault Status Register
40000000RBDRead/Write Control Register 2
5 FD US2 US1 US0 OS3 OS2 OS1 OS0 Read/Write Over/Under-Scale Register
600000G2G1G0Read/Write PGA Gain
7 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Read/Write Alarm Config. Register
8 0 VP2 VP1 VP0 0 VN2 VN1 VN0 Read/Write PGA Input Config. Register
9 0 IB2 IB1 IB0 0 IA2 IA1 IA0 Read/Write I
REF
Output Config. Register
10 FG7 FG6 FG5 FG4 FG3 FG2 FG1 FG0 Read/Write Fine I
REF
Adjust Register
11 CG7 CG6 CG5 CG4 CG3 CG2 CG1 CG0 Read/Write Coarse I
REF
Adjust Register
12 FZ7 FZ6 FZ5 FZ4 FZ3 FZ2 FZ1 FZ0 Read/Write Fine Zero Adjust Register
13 CZ7 CZ6 CZ5 CZ4 CZ3 CZ2 CZ1 CZ0 Read/Write Coarse Zero Adjust Register
14 L7 L6 L5 L4 L3 L2 L1 L0 Read/Write Linearization Adjust Register
15 S7 S6 S5 S4 S3 S2 S1 S0 Read/Write Checksum Register
Read/Write Operation
Data Bit
Assert CS2
Ignore Serial Data/A
BIT FAULT MODE
F0 Negative Input Exceeds Positive Limit.
F1 Negative Input Exceeds Negative Limit.
F2 Positive Input Exceeds Positive Limit.
F3 Positive Input Exceeds Negative Limit.
TABLE VI. Register 3, Fault Status Register.