Datasheet
2
SBOS061B
www.ti.com
XTR105
FUNCTIONAL BLOCK DIAGRAM
975Ω
6
I = 100µA +
100µA
800µA 800µA
25Ω
V+
Q
1
9
B
10
11
4
13
2
3
8
E
V
IN
R
G
I
O
= 4mA + V
IN
•
40
R
G
( )
5.1V
R
G
R
LIN
1kΩ
V
IN
+
V
IN
–
I
RET
7
V
REG
14
1
12
I
R2
I
R1
V
LIN
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
XTR105 DIP-14 N –40°C to +85°C XTR105PA XTR105PA Rails, 25
" """XTR105P XTR105P Rails, 25
XTR105 SO-14 Surface-Mount D –40°C to +85°C XTR105UA XTR105UA Rails, 58
" """XTR105UA XTR105UA/2K5 Tape and Reel, 2500
XTR105 SO-14 Surface-Mount D –40°C to +85°C XTR105U XTR105U Rails, 58
" """XTR105U XTR105U/2K5 Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
PACKAGE/ORDERING INFORMATION
(1)
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply, V+ (referenced to the I
O
pin) ...................................... 40V
Input Voltage, V
IN+
, V
IN–
(referenced to the I
O
pin) .................... 0V to V+
Storage Temperature Range .........................................–55°C to +125°C
Lead Temperature (soldering, 10s) ............................................... +300°C
Output Current Limit ................................................................ Continuous
Junction Temperature .................................................................... +165°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
Top View DIP and SO
PIN CONFIGURATION
I
R1
V
IN
R
G
R
G
NC
I
RET
I
O
I
R2
V
IN
V
LIN
V
REG
V+
B (Base)
E (Emitter)
NC = No Internal Connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
– +