Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
5 PCIe Extended Configuration Space
The programming model of the PCIe extended configuration space is compliant to the PCI Express Base
Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCIe
extended configuration map uses the PCIe advanced error reporting capability and PCIe virtual channel
(VC) capability headers.
Sticky bits are reset by a global reset (GRST) or the internally-generated power-on reset. EEPROM
loadable bits are reset by a PCIe reset (PERST), GRST, or the internally-generated power-on reset. The
remaining register bits are reset by a PCIe hot reset, PERST, GRST, or the internally-generated power-on
reset.
Table 5-1. PCIe Extended Configuration Register Map
REGISTER NAME OFFSET
Next capability offset/capability version Advanced error reporting capabilities ID 100h
Uncorrectable error status register
(1)
104h
Uncorrectable error mask
(1)
108h
Uncorrectable error severity
(1)
10Ch
Correctable error status
(1)
110h
Correctable error mask
(1)
114h
Advanced error capabilities and control
(1)
118h
Header log
(1)
11Ch
Header log
(1)
120h
Header log
(1)
124h
Header log
(1)
128h
Secondary uncorrectable error status
(1)
12Ch
Secondary uncorrectable error mask
(1)
130h
Secondary uncorrectable error severity
(1)
134h
Secondary error capabilities and control
(1)
138h
Secondary header log
(1)
13Ch
Secondary header log
(1)
140h
Secondary header log
(1)
144h
Secondary header log
(1)
148h
Reserved 14Ch FFCh
(1) This register shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
5.1 Advanced Error Reporting Capability ID Register
This read-only register identifies the linked list item as the register for PCIe advanced error reporting
capabilities. The register returns 0001h when read.
PCIe extended register 100h
offset:
Register type: Read only
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
96 PCIe Extended Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
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