Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
4.72 Arbiter Time-Out Status Register
The arbiter time-out status register contains the status of each request (request 50) time-out. The time-out
status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out
value. See Table 4-43 for a complete description of the register contents.
PCI register offset: DEh
Register type: Read/Clear
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4-43. Arbiter Time-Out Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7:6 RSVD R Reserved. Returns 00b when read.
5 REQ5_TO RCU Request 5 time-out status
0 = No time-out
1 = Time-out has occurred.
4 REQ4_TO RCU Request 4 time-out status
0 = No time-out
1 = Time-out has occurred.
3 REQ3_TO RCU Request 3 time-out status
0 = No time-out
1 = Time-out has occurred.
2 REQ2_TO RCU Request 2 time-out status
0 = No time-out
1 = Time-out has occurred.
1 REQ1_TO RCU Request 1time-out status
0 = No time-out
1 = Time-out has occurred.
0 REQ0_TO RCU Request 0 time-out status
0 = No time-out
1 = Time-out has occurred.
94 Classic PCI Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
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