Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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4.70 Arbiter Control Register

The arbiter control register controls the device's internal arbiter. The arbitration scheme used is a two-

tier rotational arbitration. The device is the only secondary bus master that defaults to the higher-

priority arbitration tier. See Table 4-41 for a complete description of the register contents.

PCI register offset: DCh

Default value: 40h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 0 0 0 0 0

Table 4-41. Arbiter Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

(1)

PARK RW Bus parking mode. This bit determines where the internal arbiter parks the secondary bus.

When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is

cleared, the arbiter parks the bus on the last device mastering the secondary bus.

0 = Park the secondary bus on the last secondary bus master (default)

1 = Park the secondary bus on the bridge

(1)

BRIDGE_TIER_SEL RW Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration

scheme.

0 = Lowest-priority tier

1 = Highest-priority tier (default)

5:1

(1)

RSVD RW Reserved. These bits are reserved and must not be changed from their default value of

00000b.

(1)

TIER_SEL0 RW GNT0 tier select. This bit determines in which tier GNT0 is placed in the arbitration

scheme.

0 = Lowest-priority tier (default)

1 = Highest-priority tier

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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