Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
4-29 Link Capabilities Register Description ........................................................................................ 77
4-30 Link Control Register Description ............................................................................................. 78
4-31 Link Status Register Description .............................................................................................. 79
4-32 Serial-Bus Slave Address Register Descriptions ............................................................................ 80
4-33 Serial-Bus Control and Status Register Description ........................................................................ 81
4-34 GPIO Control Register Description ............................................................................................ 82
4-35 GPIO Data Register Description ............................................................................................... 83
4-36 Control and Diagnostic Register 0 Description .............................................................................. 84
4-37 Control and Diagnostic Register 1 Description .............................................................................. 86
4-38 Control and Diagnostic Register 2 Description .............................................................................. 87
4-39 Subsystem Access Register Description ..................................................................................... 88
4-40 General Control Register Description ......................................................................................... 89
4-41 Arbiter Control Register Description .......................................................................................... 92
4-42 Arbiter Request Mask Register Description .................................................................................. 93
4-43 Arbiter Time-Out Status Register Description ............................................................................... 94
5-1 PCIe Extended Configuration Register Map.................................................................................. 96
5-2 Uncorrectable Error Status Register Description ............................................................................ 97
5-3 Uncorrectable Error Mask Register Description ............................................................................. 98
5-4 Uncorrectable Error Severity Register Description .......................................................................... 99
5-5 Correctable Error Status Register Description ............................................................................. 101
5-6 Correctable Error Mask Register Description .............................................................................. 102
5-7 Advanced Error Capabilities and Control Register Description .......................................................... 103
5-8 Secondary Uncorrectable Error Status Register Description ............................................................. 104
5-9 Secondary Uncorrectable Error Mask Register Description .............................................................. 105
5-10 Secondary Uncorrectable Error Severity Register Description .......................................................... 106
5-11 Secondary Error Capabilities and Control Register Description ......................................................... 107
5-12 Secondary Header Log Register Description .............................................................................. 108
6-1 Device Control Memory Window Register Map............................................................................. 109
6-2 GPIO Control Register Description .......................................................................................... 110
6-3 GPIO Data Register Description ............................................................................................. 111
6-4 Serial-Bus Slave Address Register Descriptions .......................................................................... 112
6-5 Serial-Bus Control and Status Register Description ....................................................................... 113
7-1 1394 OHCI Configuration Register Map ..................................................................................... 114
7-2 Command Register Description .............................................................................................. 116
7-3 Status Register Description ................................................................................................... 117
7-4 Class Code and Revision ID Registers Description ....................................................................... 118
7-5 Latency Timer and Class Cache Line Size Registers Description ...................................................... 118
7-6 Header Type and BIST Registers Description ............................................................................. 119
7-7 OHCI Base Address Register Description .................................................................................. 119
7-8 TI Base Address Register Description ...................................................................................... 120
7-9 Subsystem Vendor ID and Subsystem ID Registers Description ........................................................ 121
7-10 Interrupt Line and Interrupt Pin Registers Description .................................................................... 122
7-11 Minimum Grant and Minimum Latency Registers Description ........................................................... 123
7-12 OHCI Control Register Description .......................................................................................... 123
7-13 Capability ID and Next Item Pointer Registers Description ............................................................... 124
7-14 Power Management Capabilities Register Description ................................................................... 124
7-15 Power Management Control and Status Register Description ........................................................... 125
7-16 Power Management Extension Registers Description .................................................................... 125
Copyright © 2008–2013, Texas Instruments Incorporated List of Tables 9