Datasheet
XIO2213B
www.ti.com
SCPS210F –OCTOBER 2008–REVISED MAY 2013
Table 4-40. General Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:30
(1)
CFG_RETRY_ RW Configuration retry counter. Configures the amount of time that a configuration request must be
CNTR retried on the secondary PCI bus before it may be completed with configuration retry status on
the PCIe side.
00 = 25 s
01 = 1 ms
10 = 25 ms (default)
11 = 50 ms
29:28
(1)
ASPM_CTRL_ RW Active-state power-management control default override. These bits are used to determine the
DEF_OVRD power up default for bits 1:0 of the link control register in the PCIe capability structure.
00 = Power-on default indicates that the active-state power management is disabled (00b)
01 = (default).
10 = Power-on default indicates that the active-state power management is enabled for
11 = L0s (01b).
Power-on default indicates that the active-state power management is enabled for
L1s (10b).
Power-on default indicates that the active-state power management is enabled for
L0s and L1s (11b).
27
(2)
LOW_POWER _ RW Low-power enable. When this bit is set, the half-ampitude, no preemphasis mode for the PCIe TX
EN drivers is enabled. The default for this bit is 0b.
26
(1)
PCI_PM_ RW PCI power management version control. This bit controls the value reported in bits 2:0
VERSION_ CTRL (PM_VERSION) in the power management capabilities register (offset 52h, see Section 4.33). It
also controls the value of bit 3 (NO_SOFT_RESET) in the power management control/status
register (offset 54h, see Section 4.34).
0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power
Management 1.1 compliance.
1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power
Management 1.2 compliance (default).
25
(1)
STRICT_ RW Strict priority enable. When this bit is 0, the default LOW_PRIORITY_COUNT will be 001. When
PRIORITY_EN this bit is 1, the default LOW_PRIORITY_COUNT will be 000. This default value for this bit is 1.
When this bit is set and the LOW_PRIORITY_COUNT is 000, meaning that strict priority VC
arbitration is used and the extended virtual channel always receives priority over VC0 at the PCIe
port.
0 = Default LOW_PRIORITY_COUNT is 001b.
1 = Default LOW_PRIORITY_COUNT is 000b (default).
24
(1)
FORCE_MRM RW Force memory read multiple
0 = Memory read multiple transactions are disabled (default).
1 = All upstream memory read transactions initiated on the PCI bus are treated as though
they are memory read multiple transactions in which prefetching is supported for the
transaction. This bit shall only affect the XIO2213B design when the
EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is set.
23
(1)
CPM_EN_ RW Clock power-management enable default override. This bit is used to determine the power up
DEF_OVRD default for bit 8 of the link control register in the PCIe capability structure.
0 = Power-on default indicates that clock power management is disabled (00b) (default).
1 = Power-on default indicates that clock power management is enabled for L0s and L1
(11b).
22:20
(1)
POWER_ OVRD RW Power override. This bit field determines how the bridge responds when the slot power limit is
less than the amount of power required by the bridge and the devices behind the bridge. This
field shall be hardwired to 000b since XIO2213B does not support slot power limit functionality.
000 = Ignore slot power limit (default)
001 = Assert the PWR_OVRD terminal
010 = Disable secondary clocks selected by the clock mask register
011 = Disable secondary clocks selected by the clock mask register and assert the
PWR_OVRD terminal
100 = Respond with unsupported request to all transactions except for configuration
transactions (type 0 or type 1) and set slot power limit messages
101, 110, 111 = Reserved
(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
(2) These bits are reset only by a global reset (GRST) or the internally generated power-on reset.
Copyright © 2008–2013, Texas Instruments Incorporated Classic PCI Configuration Space 89
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