Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
4.65 Subsystem Access Register
The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 84h and 86h. See Table 4-39 for a complete description of the register contents.
PCI register offset: D0h
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-39. Subsystem Access Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:16
(1)
SubsystemID RW Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI
offset 86h (see Section 4.46).
15:0
(1)
SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 84h (see Section 4.45).
(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
4.66 General Control Register
This read/write register controls various functions of the bridge. See Table 4-40 for a complete description
of the register contents.
PCI register offset: D4h
Register type: Read only, Read/Write
Default value: 8600 025Fh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1
88 Classic PCI Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
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