Datasheet

XIO2213B
SCPS210F OCTOBER 2008REVISED MAY 2013
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4.62 Control and Diagnostic Register 0
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4-36 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause
interoperability or other problems.
PCI register offset: C0h
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-36. Control and Diagnostic Register 0 Description
BIT FIELD NAME ACCESS DESCRIPTION
31:24
(1)
PRI_BUS_NUM R This field contains the captured primary bus number.
23:19
(1)
PRI_DEVICE_NUM R This field contains the captured primary device number.
18 ALT_ERROR_REP RW Alternate error reporting. This bit controls the method that the XIO2213B uses for error
reporting.
0 = Advisory nonratal error reporting supported (default)
1 = Advisory nonfatal error reporting not supported
17
(2)
DIS_BRIDGE_PME RW Disable bridge PME input
0 = PME input signal to the bridge is enabled and connected to the PME signal
from the 1394 OHCI function (default).
1 = PME input signal to the bridge is disabled.
16
(2)
DIS_OHCI_PME RW Disable OHCI_PME
0 = OHCI_PME pin is enabled and connected to the PME signal from the 1394
OHCI function (default).
1 = OHCI_PME pin is disabled.
15:14
(1)
FIFO_SIZE RW FIFO size. This field contains the maximum size (in DW) of the FIFO.
13:12 RSVD R Reserved. Returns 00b when read.
11 ALLOW_CFG_ANY_FN RW Allow configuration access to any function. When this bit is set, the bridge shall respond
to configuration accesses to any function number.
10 RETURN_PW_CREDITS RW Return PW packet credits. When this bit is set, the bridge shall return all the PW packet
credits.
9 RSVD R Reserved. Returns 0b when read.
8 RETURN_CPL_CREDITS RW Return completion credits. When this bit is set, the bridge shall return all completion
credits immediately.
7 EN_CACHE_LINE_CHECK RW Enable cache line check
0 = Bridge shall use side-band signals to determine the transaction size (default).
1 = Bridge shall use the cache line size register to determine the transaction size.
(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
(2) These bits are reset only by a global reset (GRST) or the internally generated power-on reset.
84 Classic PCI Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
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