Datasheet
XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013
www.ti.com
List of Tables
2-1 7 × 7 Terminals Sorted By Ball Number....................................................................................... 16
2-2 7 × 7 Terminals Sorted Alphanumerically..................................................................................... 18
2-3 12 × 12 Terminals Sorted By Ball Number.................................................................................... 20
2-4 12 × 12 Terminals Sorted Alphanumerically.................................................................................. 22
2-5 Power-Supply Terminals ........................................................................................................ 25
2-6 Ground Terminals ................................................................................................................ 26
2-7 PCIe Terminals ................................................................................................................... 26
2-8 Clock Terminals .................................................................................................................. 26
2-9 1394 Terminals ................................................................................................................... 27
2-10 Reserved Terminals.............................................................................................................. 29
2-11 Miscellaneous Terminals ........................................................................................................ 29
3-1 XIO2213B Reset Options ....................................................................................................... 34
3-2 Initial Flow Control Credit Advertisements .................................................................................... 35
3-3 Messages Supported by Bridge ................................................................................................ 36
3-4 EEPROM Register Loading Map............................................................................................... 41
3-5 Registers Used To Program Serial-Bus Devices............................................................................. 43
3-6 Clocking In Low Power States.................................................................................................. 44
3-7 1394b OHCI Configuration Register Map ..................................................................................... 46
3-8 1394 OHCI Memory Command Options ...................................................................................... 47
4-1 Classic PCI Configuration Register Map ...................................................................................... 48
4-2 Command Register Description ............................................................................................... 50
4-3 Status Register Description .................................................................................................... 51
4-4 Class Code and Revision ID Register Description .......................................................................... 52
4-5 Device Control Base Address Register Description ........................................................................ 53
4-6 Device Control Base Address Register Description ........................................................................ 54
4-7 I/O Base Register Description ................................................................................................. 55
4-8 I/O Limit Register Description .................................................................................................. 56
4-9 Secondary Status Register Description ...................................................................................... 57
4-10 Memory Base Register Description ........................................................................................... 58
4-11 Memory Limit Register Description ............................................................................................ 58
4-12 Prefetchable Memory Base Register Description ........................................................................... 59
4-13 Prefetchable Memory Limit Register Description ............................................................................ 59
4-14 Prefetchable Base Upper 32 Bits Register Description .................................................................... 60
4-15 Prefetchable Limit Upper 32 Bits Register Description ..................................................................... 60
4-16 I/O Base Upper 16 Bits Register Description ................................................................................ 61
4-17 I/O Limit Upper 16 Bits Register Description ................................................................................ 61
4-18 Bridge Control Register Description ........................................................................................... 63
4-19 Power Management Capabilities Register Description ..................................................................... 66
4-20 Power Management Control/Status Register Description .................................................................. 67
4-21 PM Bridge Support Extension Register Description ........................................................................ 68
4-22 MSI Message Control Register Description .................................................................................. 69
4-23 MSI Message Lower Address Register Description ........................................................................ 70
4-24 MSI Message Data Register Description ..................................................................................... 71
4-25 PCI Express Capabilities Register Description .............................................................................. 73
4-26 Device Capabilities Register Description ..................................................................................... 74
4-27 Device Control Register Description .......................................................................................... 75
4-28 Device Status Register Description ........................................................................................... 76
8 List of Tables Copyright © 2008–2013, Texas Instruments Incorporated