Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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Table 4-27. Device Control Register Description (continued)

BIT FIELD NAME ACCESS DESCRIPTION

2 FERE RW Fatal error reporting enable. If this bit is set, the bridge is enabled to send ERR_FATAL

messages to the root complex when a system error event occurs.

0 = Do not report fatal errors to the root complex (default)

1 = Report fatal errors to the root complex

1 NFERE RW Nonfatal error reporting enable. If this bit is set, the bridge is enabled to send

ERR_NONFATAL messages to the root complex when a system error event occurs.

0 = Do not report nonfatal errors to the root complex (default)

1 = Report nonfatal errors to the root complex

0 CERE RW Correctable error reporting enable. If this bit is set, the bridge is enabled to send ERR_COR

messages to the root complex when a system error event occurs.

0 = Do not report correctable errors to the root complex (default)

1 = Report correctable errors to the root complex

4.52 Device Status Register

The device status register provides PCIe device specific information to the system. See Table 4-28 for a

complete description of the register contents.

PCI register offset: 9Ah

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-28. Device Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:6 RSVD R Reserved. Returns 00 0000 0000b when read.

5 PEND RU Transaction pending. This bit is set when the bridge has issued a nonposted transaction that has

not been completed.

4 APD RU AUX power detected. This bit indicates that AUX power is present.

0 = No AUX power detected

1 = AUX power detected

3 URD RCU Unsupported request detected. This bit is set by the bridge when an unsupported request is

received.

2 FED RCU Fatal error detected. This bit is set by the bridge when a fatal error is detected.

1 NFED RCU Nonfatal error detected. This bit is set by the bridge when a nonfatal error is detected.

0 CED RCU Correctable error detected. This bit is set by the bridge when a correctable error is detected.

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