Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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4.45 Subsystem Vendor ID Register

This register, used for system and option card identification purposes, may be required for certain

operating systems. This read-only register is initialized through the EEPROM and can be written through

the subsystem alias register. This register shall only be reset by a fundamental reset (FRST).

PCI register offset: 84h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.46 Subsystem ID Register

This register, used for system and option card identification purposes, may be required for certain

operating systems. This read-only register is initialized through the EEPROM and can be written through

the subsystem alias register. This register shall only be reset by FRST.

PCI register offset: 86h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.47 PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for PCIe capabilities. The register

returns 10h when read.

PCI register offset: 90h

Default value: 10h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 1 0 0 0 0

4.48 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge.

This register reads 00h indicating no additional capabilities are supported.

PCI register offset: 91h

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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