Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
4.40 MSI Message Lower Address Register
This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is
detected. See Table 4-23 for a complete description of the register contents.
PCI register offset: 64h
Register type: Read only, Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-23. MSI Message Lower Address Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:2 ADDRESS RW System specified message address
1:0 RSVD R Reserved. Returns 00b when read.
NOTE
Enabling MSI messaging in the XIO2213B has no effect.
4.41 MSI Message Upper Address Register
This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is
detected. If this register contains 0000 0000h, 32-bit addressing is used; otherwise, 64-bit addressing is
used.
PCI register offset: 68h
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NOTE
Enabling MSI messaging in the XIO2213B has no effect.
70 Classic PCI Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
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