Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
4.34 Power Management Control/Status Register
This register determines and changes the current power state of the bridge. No internal reset is generated
when transitioning from the D3
hot
state to the D0 state. See Table 4-20 for a complete description of the
register contents.
PCI register offset: 54h
Register type: Read only, Read/Write
Default value: 0008h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Table 4-20. Power Management Control/Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15 PME_STAT R PME status. This bit is read only and returns 0b when read.
14:13 DATA_SCALE R Data scale. This 2-bit field returns 00b when read since the bridge does not use the data
register.
12:9 DATA_SEL R Data select. This 4-bit field returns 0h when read since the bridge does not use the data
register.
8 PME_EN RW PME enable. This bit has no function and acts as scratchpad space. The default value for
this bit is 0b.
7:4 RSVD R Reserved. Returns 0h when read.
3 NO_SOFT_RESET R No soft reset. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register (offset
D4h, see Section 4.66) is 0b, this bit returns 0b for compatibility with version 1.1 of the PCI
Power Management Specification. If PCI_PM_VERSION_CTRL is 1b, this bit returns 1b
indicating that no internal reset is generated and the device retains its configuration context
when transitioning from the D3
hot
state to the D0 state.
2 RSVD R Reserved. Returns 0b when read.
1:0 PWR_STATE RW Power state. This 2-bit field determines the current power state of the function and sets the
function into a new power state. This field is encoded as follows:
00 = D0 (default)
01 = D1
10 = D2
11 = D3
hot
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