Datasheet

XIO2213B
SCPS210F OCTOBER 2008REVISED MAY 2013
www.ti.com
4.33 Power Management Capabilities Register
This read-only register indicates the capabilities of the bridge related to PCI power management. See
Table 4-19 for a complete description of the register contents.
PCI register offset: 52h
Register type: Read only
Default value: 0603h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1
Table 4-19. Power Management Capabilities Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:11 PME_SUPPORT R PME support. This 5-bit field indicates the power states from which the bridge may assert
PME. Because the bridge never generates a PME except on a behalf of a secondary
device, this field is read only and returns 00000b.
10 D2_SUPPORT R This bit returns a 1b when read, indicating that the function supports the D2 device power
state.
9 D1_SUPPORT R This bit returns a 1b when read, indicating that the function supports the D1 device power
state.
8:6 AUX_CURRENT R 3.3 V
AUX
auxiliary current requirements. This field returns 000b since the bridge does not
generate PME from D3
cold
.
5 DSI R Device specific initialization. This bit returns 0b when read, indicating that the bridge does
not require special initialization beyond the standard PCI configuration header before a
generic class driver is able to use it.
4 RSVD R Reserved. Returns 0b when read.
3 PME_CLK R PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.
2:0 PM_VERSION R Power-management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control
register (offset D4h, see Section 4.66) is 0b, this field returns 010b indicating revision 1.1
compatibility. If PCI_PM_VERSION_CTRL is 1b, this field returns 011b indicating revision
1.2 compatibility.
66 Classic PCI Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: XIO2213B