Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
4.21 Prefetchable Memory Base Register
This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge
forwards downstream. See Table 4-12 for a complete description of the register contents.
PCI register offset: 24h
Register type: Read only, Read/Write
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 4-12. Prefetchable Memory Base Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:4 PREBASE RW Prefetchable memory base. Defines the lowest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
00000h. The prefetchable base upper 32 bits register (offset 28h, see Section 4.23) specifies the bit
[63:32] of the 64-bit prefetchable memory address.
3:0 64BIT R 64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
4.22 Prefetchable Memory Limit Register
This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge
forwards downstream. See Table 4-13 for a complete description of the register contents.
PCI register offset: 26h
Register type: Read only, Read/Write
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 4-13. Prefetchable Memory Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:4 PRELIMIT RW Prefetchable memory limit. Defines the highest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
FFFFFh. The prefetchable limit upper 32 bits register (offset 2Ch, see Section 4.24) specifies the bit
[63:32] of the 64-bit prefetchable memory address.
3:0 64BIT R 64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
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