Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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4.11 Scratchpad RAM Base Address

This register is used to program the memory address used to access the embedded scratchpad RAM.

PCI register offset: 14h

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-6. Device Control Base Address Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:12 ADDRESS R or RW Memory address. The memory address field for XIO2213B uses 20 read/write bits indicating

that 4096 bytes of memory space are required. If the BAR1_EN bit (bit 6 at C8h) is 0, these

bits are read only and return zeros when read. If the BAR1_EN bit is 1, these bits are

read/write.

11:4 RSVD R Reserved. These bits are read only and return 00h when read.

3 PRE_FETCH R Prefetchable. This bit is read-only 0b indicating that this memory window is not prefetchable.

2:1 MEM_TYPE R Memory type. This field is read-only 00b indicating that this window can be located anywhere

in the 32-bit address space.

0 MEM_IND R Memory space indicator. This field returns 0b indicating that memory space is used.

4.12 Primary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCIe interface is

connected to.

PCI register offset: 18h

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.13 Secondary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCI interface is

connected to. The bridge uses this register to determine how to respond to a type 1 configuration

transaction.

PCI register offset: 19h

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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